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Visitor
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Registered: ‎02-12-2020

FIR IP CORE 5.0 INTERFACING OR INSTANTIATION IN USER DEFINED HDL DESIGN

Assalam u Alaikum,

Hello,

I am a new user of FPGA (Verilog) IP Cores. I have to use FIR IP Core as Hilbert Transform in my project.

My question is that how do I interface the IP Core with my project. Is there required any interface code or just I have to instantiate the Core to my project, and if so how do I instantiate it in my programme file.

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Moderator
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Registered: ‎08-16-2018

Re: FIR IP CORE 5.0 INTERFACING OR INSTANTIATION IN USER DEFINED HDL DESIGN

HI @kashifminhas 

 

You will get the instantiatian template when you add the IP from the IP-catalaog. 

Please look at the .vho file in the below figure. You can copy-paste in your main design to instantiate the FIR.

 

 Screenshot_14.jpg

 

 


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