FIR IP CORE 5.0 INTERFACING OR INSTANTIATION IN USER DEFINED HDL DESIGN
Assalam u Alaikum,
I am a new user of FPGA (Verilog) IP Cores. I have to use FIR IP Core as Hilbert Transform in my project.
My question is that how do I interface the IP Core with my project. Is there required any interface code or just I have to instantiate the Core to my project, and if so how do I instantiate it in my programme file.