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tkontogiorgis
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Registered: ‎09-10-2019

FIR compiler

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Hello,

I would like to do some DSP questions related with this post :https://forums.xilinx.com/t5/Versal-and-UltraScale/ZCU111-Capabillities/m-p/1113092#M14096

As far as i understand FIR compiler does interpolation by data width converting not by changing sample rate. Can  be confirmed?  Is there any configuration that can with the same data-width (and different clock) interpolate my data?

Also, in System Generator FIR compiler component seems a little different in the clocking section (correct me if wrong).  Can it be confirmed ? Also, what are the differences?

 

Thank you,

Theo

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vkanchan
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Registered: ‎09-18-2018

@tkontogiorgis ,

The FIR compiler comes with a demo test bench that will demonstrate the features of the core. Configure the FIR filter as interpolation filter and run the demo.

However it would be beneficial if you could take a look at configuring the "Hardware Oversampling Specifications" in the GUI, that are important for FIR configurations.

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calibra
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Registered: ‎06-20-2012

FIR Compiler can change sample rate.

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tkontogiorgis
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Hello @calibra ,

Can you confirm an example?

Is this done by having i.e twice clock frequency from input sampling frequency and interpolation x2 ?

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vkanchan
Xilinx Employee
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Registered: ‎09-18-2018

@tkontogiorgis ,

The FIR compiler comes with a demo test bench that will demonstrate the features of the core. Configure the FIR filter as interpolation filter and run the demo.

However it would be beneficial if you could take a look at configuring the "Hardware Oversampling Specifications" in the GUI, that are important for FIR configurations.

View solution in original post

thmav
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Registered: ‎01-20-2021

Hello vkanchan,

 

Could you point out where is this demo?

 

Thanks

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tkontogiorgis
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Registered: ‎09-10-2019

Hello @thmav ,

I think you can find the demo by generating the IP core from Vivado. When IP core is generated it generates the Test Bench in Simulation Sources .

Capture.PNGCapture2.PNG

 

Best Regards,

Theo

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thmav
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Registered: ‎01-20-2021

Hello @tkontogiorgis,

I even do not see the testbench generated by Vivado. I am using Vivado 2020.2 with FIR Compiler 7.2 on Windows 10 64b.

Could you point out a working example using FIR Compiler 7.2? I have tried the xapp1161, I have managed (with some change in the generate_vivado_project.tcl file) to Elaborate and Synthesis but I can not make the behavioral Simulation work using xsim.

Thank you.

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tkontogiorgis
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Hello @thmav ,

After you generate the IP from Vivado IP Catalog you should have those files. You can find them in Vivado_Project_Name\Vivado_Project_Name.srcs\sources_1\ip\fir_compiler_0\demo_tb 

After that you can run simulation in Vivado. I don't know if anything has changed from my Vivado 2019.1 but with in my version I worked in this way.

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thmav
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Registered: ‎01-20-2021

Hello @tkontogiorgis 

I don't see that.

Could you point out a working example of FIR Compiler? I have tried xapp1161 but the simulation has not worked although I manage to work around on the generate_vivado_project.tcl to Elaborate.

Thank you. 

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tkontogiorgis
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Registered: ‎09-10-2019

Mmmm strange. Perhaps @vkanchan can help you more. I just wanted to inform you about the current testbench provided by Xilinx. I am not aware of other working examples. 

Best Regards,

Theo

 

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @thmav ,

Are you using the FIR compiler in IPI mode ? If so, it will not generate the test bench. 

For test bench, just add the IP from Vivado IP catalog to the sources window and generate the output products. You should then see the test bench as mentioned in the previous threads.

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