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Visitor
Visitor
14,198 Views
Registered: ‎12-13-2007

FIR with MAC generated by IP Core Gen Filter Compiler v3.2: width I/O Problem

I want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter.
 
My problem is about I/O in the block of filter generated from IP core generator.
 
I would the same bit lenght of the input, in output, for connections I/O.

In input i have DATA_IN [9 0] and instead DATA_OUT [30 0].
I would [9 0] for output!

FILTER is a FIR 21 TAPS with MAC, is there a solution for truncate bit?
 
Can you help me?
 
Thanks so much.
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Visitor
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Registered: ‎12-13-2007

I think, i can do a filter output rounding. Can i make it from 31 bits to 10 bits? Do I loss bits information?
  • DATAIN 10 bits precision  [9 downto 0]
  • TAPS 21
  • DATAOUT 31bits  [30 downto]

 

 It is desiderable to limit the output sample width of the filter to minimize resource utilization in downstream blocks in a signal processing chain.

So i would DATAOUT like DATAIN 10 bits precision [9 downto 0]

 

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Xilinx Employee
Xilinx Employee
14,182 Views
Registered: ‎08-07-2007

There is bit growth through the filter on acocunt of the multiplication that occurs for each tap of your filter.  The output width is worst case and will avoid loss of data due to truncation.  If your downstream processing stream requires a lesser bit width then you need to slice off the bits your're interested in and pass those down stream.  You can leave the remaining bits unconnected on the filter output.  I would suggest you perform some rounding when you slice off your bits to avoid a DC shift.
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Xilinx Employee
Xilinx Employee
14,179 Views
Registered: ‎08-02-2007

Page two of the FIR GUI could be useful as well.  It allows you to specify the input, output, and coefficient widths.  If you specify the output rounding mode that suits your application (there are tradeoffs for each one, refer to the datasheet), you can then specify the output width of the core.
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Visitor
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Registered: ‎12-13-2007

thanks so much
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Visitor
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14,173 Views
Registered: ‎12-13-2007

I've seen FIR GUI (the second page), but i cant' set "output rounding mode", i use xilinx spartan II family fpga   :-( ???
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Visitor
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Registered: ‎12-13-2007

I explain to you my STEPS:
  1. I use Filter Design Analysis FDA Matlab Toolboxes, for .coe file creation. When i set parameters filter quantization, i can decide to specify precision, output rounding, signed ora unsigned coefficient etc etc. I choose:
    • 21 taps lowpass fir filter with window kaiser beta=0.5 
    • fs=40 mhz,  
    • fpass=10mhz
    • coeff width 16 bits, signed, fixed point,
    • datainput 10 bits, output 10bits with rounding convergence mode
  2. After I use ISE 9.2i - IP CORE GENERATOR Filter Compiler 3.2i for my XILINX XC2S200 SPARTAN II FAMILY
    •  insert .coe file and set coefficient parameter, but there is not a solution, in the second step, i cant't select rounding output mode!
    •  After matlab toolboxes settings, an other time, i must select sampling frequency, clock frequency and so on... is it normal?
    • The information i think is in the .coe file...isn't it? Instead i must insert the same parameters in filter compiler but not output rounding mode :-(

 

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Visitor
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Registered: ‎12-13-2007

  • I'm working for a thesis, is there a solution for my problem, please? Must I operate on the code, manually? What?  Isn't an automatic option for filter output truncation (output rounding mode) for my spartan II xc2s200 ?

 

  • Is there a block diagram which describes the MAC structure of filter and specify the code? for example, what is the structure which contains code block VCC, GND, FDCE, XORCY, MULT_AND, LUT4, etc.... block diagram connections?? (The code is generated from filter compiler code, in the datasheet there is generic mac structure!) The code is in attachment.
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