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prateekj212

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11-09-2018 03:06 AM

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Registered:
04-10-2018

Fixed Point signed multiplier and adder tree

Hi,

I am trying to implement a parameterised signed signed point multiplier in Verilog for a FPGA acceleration of a Convolutional Neural Network. My inputs to the multiplier will be fixed point numbers in the Q8.9 (8 bits integer, 9 bits fractional part,1 bit sign),lets say. I want to write code such that 25 such multipliers are working in parallel to produce 25 product terms which will then be added in a adder tree. Now, I know that multiplication of two 18 bit numbers will produce a 36 bit result. The problem I am facing is regarding handling the overflow after multiplication and rounding the result to again 18 bits, which feeds to the adder tree.

After doing some research on Fixed point multiplication, I have figured out that I would get a Q16.18 result of which I can part select the middle part for my result. But I would be losing precision in the lower fractional bits. Now as for the rounding of the integer part, I want to detect the overflow from the inferred DSP block. Is this possible? If yes, how? Here is what i have tried so far. I am fairly new to verilog so any help would be greatly appreciated.

I can provide further clarifications if my questions lacks clarity.

(* use_dsp = "yes" *) module pe_mult(clk,reset,in_a,in_b,out); parameter data_size=18; input wire reset,clk; input [data_size-1:0] in_a,in_b; output [2*data_size-1:0] out; (* dont_touch = "true" *) reg [data_size-1:0] in_a_reg,in_b_reg; (* dont_touch = "true" *) reg [2*data_size-1:0] out_reg; always @(posedge clk)begin if(reset) begin //out=0; in_a_reg <=0; in_b_reg <=0; out_reg <= 0; end else begin in_a_reg <= in_a; in_b_reg <= in_b; out_reg <= in_a_reg * in_b_reg; out_reg <= out_reg << 1'b1; end end assign out = {out_reg[35],out_reg[25:9]}; endmodule

Regards

Student

2 Replies

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bruce_karaffa

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11-09-2018 05:14 AM

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Registered:
06-21-2017

I'm not sure why you think you can pick the middle bits. If your inputs to the multiplier are close to full scale, you will need all of the integer bits out of the multiplier to represent the output.

If you want to detect overflow, check the sign bit of the part of the output that you want to keep. It should be the same as all of the more significant bits that you want to drop. In most instances, if I detect an overflow, I clip to positive or negative maximum based on the most significant bit out of the multiplier or adder.

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prateekj212

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11-09-2018 05:23 AM

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Registered:
04-10-2018

@bruce_karaffa wrote:I'm not sure why you think you can pick the middle bits. If your inputs to the multiplier are close to full scale, you will need all of the integer bits out of the multiplier to represent the output.

If you want to detect overflow, check the sign bit of the part of the output that you want to keep. It should be the same as all of the more significant bits that you want to drop. In most instances, if I detect an overflow, I clip to positive or negative maximum based on the most significant bit out of the multiplier or adder.

I am not sure I follow. Could you elaborate with a verilog code?

Thank you