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Contributor
Contributor
2,469 Views
Registered: ‎04-12-2017

Floating Point IP timing constraints

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Hi,

 

I'm working on a simple project using some Xilinx floating point ip cores (adders, subtractors, accumulators, reciprocals). The goal is to calculate pi and output the result via UART using a microblaze.

 

The design works fine in the behavioural and the post synthesis functional simulation however, during the post implementation functional simulation, some of the cores return completely erratic results (something like 0 + 3 = 7?!).

 

According to the datasheet of the core, there are no special timing constraints needed, so my timing constraints just consist of a primary clock, the automatic contraints generated by my PLL and some max delays for the RXD and TXD lines. All timing constraints are being met, there's still plenty of positive slack left.

 

I would be glad if someone could give a me hint how to solve this problem.

 

Thank you,

Stephan

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1 Solution

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Contributor
Contributor
3,257 Views
Registered: ‎04-12-2017

Re: Floating Point IP timing constraints

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I solved the problem. Fixed-point did the trick!
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5 Replies
Scholar austin
Scholar
2,463 Views
Registered: ‎02-27-2008

Re: Floating Point IP timing constraints

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r,

 

Vivado or ISE?

 

You need to look for and find the complete or verbose timing report and examine the paths not constrained.  Should they be?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
2,427 Views
Registered: ‎08-01-2008

Re: Floating Point IP timing constraints

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can you please share your project. The core also provide demo_tb which you can use for running simulation.

Check the data format in product guide. Share your design so i will try to run at my end
Thanks and Regards
Balkrishan
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Contributor
Contributor
2,409 Views
Registered: ‎04-12-2017

Re: Floating Point IP timing constraints

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Hi,

 

Thanks for the help. How should I share my project (almost 1GB of data)?

The data format is correct. Some of the cores return correct results while others don't.

By the way, I'm using a Digilent Nexys Video powered by an Artix 7 xc7a200tsbg484-3.

 

Thank you,

Stephan

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Contributor
Contributor
2,294 Views
Registered: ‎04-12-2017

Re: Floating Point IP timing constraints

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Hi,

 
I uploaded my project to my Google Drive, you can find it here:

 

https://drive.google.com/file/d/0B151BpeVrhk7MUgtRUZSTGg2b00/view?usp=sharing

 

In the test bench, there is an output called "result", which should converge to a value of 0,785398 (pi / 4). This is the case in the behavioural and the post synthesis functional simulation but not in the post implementation functional simulation. All of the floating point values are represented using the IEEE754 double precision format.

 

I would be glad if someone could help me with this problem.

 

Thank you,

Stephan

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Contributor
Contributor
3,258 Views
Registered: ‎04-12-2017

Re: Floating Point IP timing constraints

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I solved the problem. Fixed-point did the trick!
0 Kudos