cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
DrTCB
Newbie
Newbie
577 Views
Registered: ‎08-18-2020

GFlops Performance and Power Dissipation of RT Kintex UltraScale FPGA?

What is the achievable GFlops (in terms of single precision 32 floating point ops) performance of the RT Kintex FPGA using Xilinx's most efficient configuration compiler?

What is the maximum power dissipation of this FPGA?

Thanks in advance,

Tom

0 Kudos
2 Replies
tenzinc
Moderator
Moderator
420 Views
Registered: ‎09-18-2014

Both depends on your design and need to be calculated. For performance you need to manually do this. See the reference below. You can get logic count including DSP block and max clock frequency from the RT datasheet. For power you need to use a estimator tool like XPE. 

 

https://www.hpcwire.com/2012/04/16/latest_fpgas_show_big_gains_in_floating_point_performance/

 

https://www.xilinx.com/products/technology/power/xpe.html

 

For power



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

------------------------------------------------------------------------------------------------

DrTCB
Newbie
Newbie
374 Views
Registered: ‎08-18-2020

tenzinc,

Thanks for your reply and the references.  I was hoping for more recent HPC design examples that provided TFLOPS counts in the UltraScale FPGA family, but if these aren't available, the references you supplied (and others) are a starting point for estimating TFLOPS/W performance numbers.

DrTCB

 

0 Kudos