08-18-2020 12:33 PM
What is the achievable GFlops (in terms of single precision 32 floating point ops) performance of the RT Kintex FPGA using Xilinx's most efficient configuration compiler?
What is the maximum power dissipation of this FPGA?
Thanks in advance,
10-14-2020 02:40 PM
Both depends on your design and need to be calculated. For performance you need to manually do this. See the reference below. You can get logic count including DSP block and max clock frequency from the RT datasheet. For power you need to use a estimator tool like XPE.
10-20-2020 07:32 AM
Thanks for your reply and the references. I was hoping for more recent HPC design examples that provided TFLOPS counts in the UltraScale FPGA family, but if these aren't available, the references you supplied (and others) are a starting point for estimating TFLOPS/W performance numbers.