UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor caro@lin2a
Visitor
2,725 Views
Registered: ‎11-02-2018

HLS in Sysgen

Jump to solution

 

Hi

 

I wrote a function in HLS and it worked correctly. C Simulation and Co-simulation also gave the desired answers.

My problem is, when the code is exported for sysgen, output was not correct.

 

The function is very simple. An array of 174 samples is fed as input and the output should be an array of 200 samples.

Output consists of two parts. First part is a preknown 26 sample array attached to the 174-sample input.

 

Could you please help me?

Associated files for both HLS environment(2017.4) and Matlab(R2017b) are attached.

 

Regards.

 

 

 

 

 

Picture.png
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
2,468 Views
Registered: ‎08-16-2018

Re: HLS in Sysgen

Jump to solution

caro@lin2a

 

1. I am getting the correct results. I attached the graph and .mat file of the result. 

2. I run the files which you attached in the beginning of the post. 

First, I generated the sysgen-project using HLS files. 

Next, imported that to Sysgen design. 

3. I attached the 'init.m' file, please run the design with this init.m file (where I added zero in the beginning). 

4. Can you try to rebuild the project using the original 'zip' files. 

 

Screenshot_4.jpg
14 Replies
Xilinx Employee
Xilinx Employee
2,609 Views
Registered: ‎09-18-2018

Re: HLS in Sysgen

Jump to solution

Hi,

I have downloaded the files that you shared to check them. Extracting them results in an error. Can you please check and share them again.

0 Kudos
Visitor caro@lin2a
Visitor
2,574 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution
Dear vkanchan
I used winrar 5.50 (64-bit) to compress these files.
I downloaded them and check again. They were Ok.
I think, winrar with lower version may not open files compressed with this version.
I thank you very much and apologize for version miss mach.
Regards.
0 Kudos
Visitor caro@lin2a
Visitor
2,547 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

Dear vkanchan

In addition, files were attached non compressed for ease.

Because, number of files to attached is limited, first HLS files are sent in this post and in the next post, HLS files will be sent.

Thank you very much.

Regards

 

0 Kudos
Visitor caro@lin2a
Visitor
2,543 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

Dear vkanchan

In this post, SysGen files were attached.

Thank you very much.

Regards

0 Kudos
Xilinx Employee
Xilinx Employee
2,535 Views
Registered: ‎09-18-2018

Re: HLS in Sysgen

Jump to solution

Hi,

Thank you for sharing the file. I will check them.

Regards,

Vivek

 

0 Kudos
Moderator
Moderator
2,495 Views
Registered: ‎08-16-2018

Re: HLS in Sysgen

Jump to solution

caro@lin2a

1. I did not go through the logic, but following change in 'init.m' will remove the error,

% (i.e. add zeroes in the beginning)

inData              = [zeros(26, 1); Data];  

 

2. Checked with below command and have 0 errors. 

>> sum(out_Correct_mFile - outSysGen(102:301)) 

0

0 Kudos
Visitor caro@lin2a
Visitor
2,474 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

 

Dear meherp

Thank you very much for considering my question.

I followed your suggestions by adding zeros to data at the beginning. But unluckily, error exists. Error can be observed both by plotting as bellow

 

plot([out_Correct_mFile, outSysGen(102:301)])

Results.png

As seen, just some first samples are the same and the rest differ.

or by typing the following command:

 

isequal(outFrame, outSysGen(102:301))

 which results to ‘0’ representing non equality. Using summation sounds not safe way of equality testing i guess.

 Edited version of files are attached.

Regards.

 

 

0 Kudos
Moderator
Moderator
2,469 Views
Registered: ‎08-16-2018

Re: HLS in Sysgen

Jump to solution

caro@lin2a

 

1. I am getting the correct results. I attached the graph and .mat file of the result. 

2. I run the files which you attached in the beginning of the post. 

First, I generated the sysgen-project using HLS files. 

Next, imported that to Sysgen design. 

3. I attached the 'init.m' file, please run the design with this init.m file (where I added zero in the beginning). 

4. Can you try to rebuild the project using the original 'zip' files. 

 

Screenshot_4.jpg
Visitor caro@lin2a
Visitor
2,433 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

 

Dear meherp

Your guidance was great. I got correct answer too.

Nice point in solving the problem was pre-adding zero to data.

Failure to get correct answer was my carelessness to addition of two delay sample to the second version of .slx file.

one delay ha been added to the enable port and the other one was at the output port.

I thank you very much.

Regards.

Edited version of files were attached so that anyone interested can use.

 

 

 

Xilinx Employee
Xilinx Employee
2,377 Views
Registered: ‎09-18-2018

Re: HLS in Sysgen

Jump to solution

HI,

To check the performance of the System Generator block generated from the HLS function, you need to pass the same test input data that you are passing the test bench in HLS. The test data input to the C function was just an array of 174 data bits and this are to be passed to the Sysgen block as well. It is not correct to manipulate the test vector by adding additional zeros before or after the data bits.

To understand how the HLS block is mapped to the System Generator block , you have to consider the mapping of input / output interface and C functions to hardware level ports and modules. In your HLS, the input and output stream functions are mapped to ap_FIFO interface in Sysgen block. That means those interfaces now accept the input data from a FIFO. The way to test the HLS block is to add a FIFO block in the sysgen design and fill in the FIFO with your test data bits. The HLS sysgen block will now read the data bits from the FIFO when the function requires it by enabling the read signal on its output interface. The function outputs Barker code bits for first 26 samples; then starts reading the test data from the FIFO and appends the data bits to output for next 174 cycles.

Please see the attached .slx file which I have created to test your HLS function. Please see the attached result which is same as your expected result.

output.jpg

you can check the result by command : plot([out_Correct_mFile,outSysGen(61:260)].

0 Kudos
Visitor caro@lin2a
Visitor
2,358 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

Dear vkanchan

I read your useful guidance and saw .slx file.

The point that there is no need to add zero at the beginning was nice.

Including FIFO to make similarity was also interesting.

But unfortunately i could not get result and the scope displayed as bellow:

Scope.png

 

i would be pleased if you could explain a little more so that i could get result out of it.

Regards

0 Kudos
Xilinx Employee
Xilinx Employee
2,210 Views
Registered: ‎09-18-2018

Re: HLS in Sysgen

Jump to solution

Hi,

The reason FIFO is added there is to supply the test vector values as present in your HLS design. In the HLS design, the test vector provided to the core are Din bits(174 bits), but in here by adding zeros ahead causes the Din to be supplied with 200bits which deviates from your test case. 

Ideally the array in your HLS gets mapped to FIFO interface in Hardware as the Stream interface is selected. Hence the test vectors need to be provided from a FIFO as mentioned in the HLS user guide.

Regarding the model, can you please tell me if  you are observing any error in executing the model. I have checked the model and attached the result window. Pls let me know if there is any error.

0 Kudos
Visitor caro@lin2a
Visitor
2,096 Views
Registered: ‎11-02-2018

Re: HLS in Sysgen

Jump to solution

Dear 

 

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
2,079 Views
Registered: ‎09-18-2018

Re: HLS in Sysgen

Jump to solution

Hi,

The reason for this is this because the step size in the step sources,connected to ap_rst and ap_start port is set 50. Please change it 50/100e6, where 100e6 is the Fs in your design. For simplicity I have changed the Fs to 1 when I tried it and hence step size  of step sources is 50. Now since Fs is different in your design, please modify the step sources by changing step size to 50/Fs.

I have checked it and it is working. 

0 Kudos