09-24-2019 05:48 AM - edited 09-25-2019 01:47 AM
I designed a simple adder in Sys Gen. I attached the project with this post.
The synthesis failed unable to meet the timing constrains. The fpga clock period = 10ns and system period =1. (default).
Board: zcu111 xczu28dr
Compilation: Hardware co-simulation JTAG
Everything seems to be related with the JTAG Clock. How should I start debugging this? What does this mean? Any help is appreciated.
09-24-2019 05:54 AM
Cant see on the phone,
but it looks liek you have an asyncornous design there,
no clocked registers ,
Timming slack / hold works to a clock,
09-24-2019 07:51 AM
I am giving the clock inside the sys gen token. The sys gen will automatically generate clock enables based on system period and fpga clock in the hardware. So I guess it is a synchronous design. Please correct me if I am wrong. Also the input is sampled at the same rate as FPGA.
The timing errror does not occur for compilation type 'ipcatalog' but only for 'Hardware cosim- JTAG
Also Hardware cosimulation does not provide expected results.
=============================================================================================== Output: z Atleast one mismatch ( with dont care into consideration) found at cycle : 2 Number of simulation mismatches = 20 Simulation mismatches: ---------------------- Cycle Expected values Actual values 2 2.0000000000000000 1.0000000000000000 3 4.0000000000000000 1.0000000000000000 4 6.0000000000000000 1.0000000000000000 5 8.0000000000000000 1.0000000000000000 6 10.0000000000000000 1.0000000000000000 7 12.0000000000000000 1.0000000000000000 8 14.0000000000000000 1.0000000000000000 9 16.0000000000000000 1.0000000000000000 10 18.0000000000000000 1.0000000000000000 11 20.0000000000000000 1.0000000000000000 12 0.0000000000000000 1.0000000000000000 13 0.0000000000000000 1.0000000000000000 14 0.0000000000000000 1.0000000000000000 15 0.0000000000000000 1.0000000000000000 16 0.0000000000000000 1.0000000000000000 17 0.0000000000000000 1.0000000000000000 18 0.0000000000000000 1.0000000000000000 19 0.0000000000000000 1.0000000000000000 20 0.0000000000000000 1.0000000000000000 21 0.0000000000000000 1.0000000000000000
09-25-2019 08:07 AM
09-25-2019 08:19 AM
hope some one else can pick this up
09-25-2019 09:12 AM
It's been years since I have done sysgen co-sim, but it looks like the timing errors are between your local 10nS clock and the JTAG clock which "should" be hidden from you since the fact your co-sim is using a JTAG link to move information betwen the FPGA and simulink is supposed to be under the hood. Perhaps changing a setting such as the clock set to single step or the co-sim interface for burst mode may fix your problem.
09-26-2019 03:03 AM - edited 09-26-2019 03:05 AM
Thank you for your reply!
I tried using the burst mode. The outptut is all zero. Still I am having timing errors. The differences I see is,
clk_out1_hwcosim_top_sys_clk_wiz_0 (inter and intra, hold and setup) negative slack has increased a bit but the timing values wrt jtag clock has not changed.
I am also a getting critical warning when I open the timing summary. I do not know if that has anything to do with the problem. I have created a separate post for that. Maybe you can take a look.
Also I observed, I set a clock 10ns in the sys gen design but I see the block diagram generated by sys gen has a 50MHz clock instead of a 100MHz clock.And I see jtag clock is 33.33ns in the timing constraints
I do not really undertstand how to see inside the connection between jtag and simulink through vivado and debug all this. It seems really really complicated. The examples in the user guides do not mention any such errors and hwcosim gives expected results in these docs. I do not know what I am doing wrong.
09-26-2019 06:05 AM
Hmmm, this really needs a recent sysgen user (or even better a Xilinx employee!) to help you out. It does seem to me to be a bug of some kind where you should not be getting these problems. (i.e. Sygen should be taking care of all this without your knowledge thus why there is no documentation on this stuff)
If you are not already, I would recommend you make sure you are using the latest version of the tools. . (The first thing a Xilinx person will probably ask is you do this anyway)
Also, (assuming this is still the same as a few years back) it’s important to match the Xilinx version against a specific Matlab version. So, make sure you are following this as well! (I definitely remember getting some random issues when not linking matlab/Xilinx versions correctly!)
09-26-2019 07:30 AM
09-26-2019 08:12 AM
Yes, you can use the ILA to test your design. All you need to do is add a "test generator" into your design to drive the adder inputs which can either be a simple constants or something more elaborate such as 2 counters. (i.e. currently you data source in from matlab)
The applications for co-sim are more about when you:
1) Are using it to acceleate your Matlab simulation (i.e. Running algorithm in FPGA will be faster than in Matlab using sysgen tokens)
2) Initial testing where you want to compare your original Matlab model vs the sysgen design side by side looking for differences/errors
3) Initial testing where you have a complex data source modeled by Matlab and want these injected into your co-sim design. This is a nice feature of co-sim since you do not need to do something messy like for example taking a seconds worth of model source data and somehow get it into your design via another means (e.g. storing it into DRAM which then needs a DRAM IF in the FPGA to move this into your adder)
So, what you are trying to do is valid since this "should" have been plug and play, but for your simple adder without all the extra complexity mentioned above for a larger design/algorithm moving strait to ILA is a better way forward than co-sim. Just keep in mind the use cases above for the future.
09-26-2019 08:15 AM
09-26-2019 08:19 AM
09-26-2019 08:28 AM
Oh, and one final thought why I am here...
If you have not already, I would look at Xilinx HLS (i.e. C to gates) instead of sygen as your bridge from DSP/Matlab into gates. In my opinion this is a far better tool (I was never a big fan of Sysgen!)
I also think sysgen may have a very limited user base these days (I guess the lack of replies to this thread backs up this claim!) which should suggest to you that there may be a better way these days! (i.e. HLS is much newer than Sysgen) :)
09-27-2019 01:42 AM