10-17-2011 08:42 AM
I would like to know how to use the FFT v6.0 in the Xilinx blockset properly as the output is always 0.
Could someone please let me know how to go about it?
The input (real) is an array of [1,0,1,0,1,0,1,0] and the imaginary part of the input is 0.
There aren't any errors as such but the output is 0.
Thank you
10-19-2011 06:55 AM - edited 10-19-2011 06:56 AM
You don't want to increast the latency of the block... you want to increase your simulation time to compensate for block latency.
Given the state of your control signals, I would agree with eilert that you should increase your simulation time. Or possibly, your control signals are not implemented correctly. Be sure you're referencing the datasheet for timing diagrams when interfacing to this core.
10-17-2011 11:12 PM
Hi,
one little hint for first time tests of FFTs:
Try feeding it with a dc-signal like : [1,1,1,1,1,1,1,1] constantly!
The result should be N*1 on the first output line, where N is the number of input samples (probably 8 in your case).
Also check the latency of the core. Maybe you just need to add some simulation time, before you can see any results coming out of the core.
Have a nice simulation
Eilert
10-18-2011 02:19 AM
i will surely try it but i have a few more doubts
-Where should I increase the latency? In the FFT block is it?
-The busy flag is always 0 and valid out is also 0.So am i to assume that the output is not right?
-Does the position of binary point matter?
I did try to give a sine wave input but it still did not work as in all the output values were zeros.
I set the option as radix 2 burst I/O
Thank you so much for helping me with this :)
10-19-2011 06:55 AM - edited 10-19-2011 06:56 AM
You don't want to increast the latency of the block... you want to increase your simulation time to compensate for block latency.
Given the state of your control signals, I would agree with eilert that you should increase your simulation time. Or possibly, your control signals are not implemented correctly. Be sure you're referencing the datasheet for timing diagrams when interfacing to this core.
10-19-2011 07:58 AM
Yes increasing it worked.
thank you both sooo much :)
06-05-2013 08:48 AM
06-05-2013 12:24 PM