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Observer aparna
Observer
5,564 Views
Registered: ‎10-17-2011

Help with the FFT block of system generator.

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I would like to know how to use the FFT v6.0 in the Xilinx blockset properly as the output is always 0.

Could someone please let me know how to go about it?

The input (real) is an array of [1,0,1,0,1,0,1,0] and the imaginary part of the input is 0.

There aren't any errors as such but the output is 0.

Thank you

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1 Solution

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Xilinx Employee
Xilinx Employee
6,144 Views
Registered: ‎08-02-2011

Re: Help with the FFT block of system generator.

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You don't want to increast the latency of the block... you want to increase your simulation time to compensate for block latency.

 

Given the state of your control signals, I would agree with eilert that you should increase your simulation time. Or possibly, your control signals are not implemented correctly. Be sure you're referencing the datasheet for timing diagrams when interfacing to this core.

www.xilinx.com

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6 Replies
Teacher eilert
Teacher
5,557 Views
Registered: ‎08-14-2007

Re: Help with the FFT block of system generator.

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Hi,

one little hint for first time tests of FFTs:

 

Try feeding it with a dc-signal like : [1,1,1,1,1,1,1,1] constantly!

The result should be N*1 on the first output line, where N is the number of input samples (probably 8 in your case).

 

Also check the latency of the core. Maybe you just need to add some simulation time, before you can see any results coming out of the core.

 

Have a nice simulation

  Eilert

 

 

Observer aparna
Observer
5,553 Views
Registered: ‎10-17-2011

Re: Help with the FFT block of system generator.

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i will surely try it but i have a few more doubts

 

-Where should I increase the latency? In the FFT block is it?

-The busy flag is always 0 and valid out is also 0.So am i to assume that the output is not right?

-Does the position of binary point matter?

 

I did try to give a sine wave input but it still did not work as in all the output values were zeros.

I set the option as radix 2 burst I/O

 

Thank you so much for helping me with this :)

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Xilinx Employee
Xilinx Employee
6,145 Views
Registered: ‎08-02-2011

Re: Help with the FFT block of system generator.

Jump to solution

You don't want to increast the latency of the block... you want to increase your simulation time to compensate for block latency.

 

Given the state of your control signals, I would agree with eilert that you should increase your simulation time. Or possibly, your control signals are not implemented correctly. Be sure you're referencing the datasheet for timing diagrams when interfacing to this core.

www.xilinx.com

View solution in original post

Observer aparna
Observer
5,535 Views
Registered: ‎10-17-2011

Re: Help with the FFT block of system generator.

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Yes increasing it worked.

thank you both sooo much :)

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Visitor mrahmadi
Visitor
4,945 Views
Registered: ‎06-05-2013

Re: Help with the FFT block of system generator.

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hi 

I have problems in the disposal of fft block of system generator

Please advise me

Thanks

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Xilinx Employee
Xilinx Employee
4,935 Views
Registered: ‎08-02-2011

Re: Help with the FFT block of system generator.

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Please create a new thread for your issue since it appears to be different.

Also, please include a description of why the core is not behaving as expected. Screenshots are helpful!
www.xilinx.com
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