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Participant luckfyzhang
Participant
641 Views
Registered: ‎10-14-2017

How can I ensure lower DSP resource utilization comparing with pure HDL coder model?

Hi,everyone:

  I am about to build a QPSK modulator and one corresponding demodulator on my Zedboard. I noticed that MathWorks have provided relative support on it, including Communications Toolbox Support Package for Xilinx Zynq-Based Radio, and reative examples, HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364. They do provide support for Zedboard. However, it is reported that their model occupy more than 63% percent of XC7z020 DSP resource utilization. It would be impossible for me to instantialize another model (AD9361 is a kind of two channels transceiver). 

So by using System generator method or HLS method with to build similar model can I ensure lower DSP resource utilization?

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3 Replies
Moderator
Moderator
570 Views
Registered: ‎08-01-2007

回复: How can I ensure lower DSP resource utilization comparing with pure HDL coder model?

To save DSP resources utilization is really a question of how you build your design. Take a FIR filter for example, if the input sample rate is 100Mbps, the clock frequency of DSP48 slice runs at 300MHz, so you will only use 1/3 DSP48 slices compared to a design with the input sample rate is 100Mbps and the clock frequency of DSP48 slice is 100MHz. Hope this can give you some clues.

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Participant luckfyzhang
Participant
566 Views
Registered: ‎10-14-2017

回复: How can I ensure lower DSP resource utilization comparing with pure HDL coder model?

Thanks for your reply. So you mean the resources utilization should not vary much with different coding platform?
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Moderator
Moderator
542 Views
Registered: ‎08-01-2007

回复: How can I ensure lower DSP resource utilization comparing with pure HDL coder model?

You will definitely see the difference, but it's not big compared to how the design is built. Sysgen will definitely will the smallest number of DSP slices compared to the other tools.

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