05-28-2020 03:03 PM
I want to implement an AWG on the FPGA. I don't know however where to start. I have some Xilinx boards at hand like Zybo, ZedBoard and the mighty ZCU102.
Does Xilinx provide an IP for that?
Do I have to code and wirte a costume IP?
The example that I like to implement is as follows, I specify a signal time and amplitude in DDR, AWG reads the values, and pass it to the DSP.
P.S. 1. Does the flow in my example correct?
P.S. 2. I know there is no ADC/DAC on the above mentioned board, I got stuck still before the DAC.
Any comment is highly appreciated.
All the best
05-28-2020 05:08 PM - edited 05-28-2020 05:15 PM
The free IP called the DDS Compiler can be used to generate waveforms. Details of this IP are given in document, PG141, and an overview is given at the following site.
Specifically, the DDS Compiler will help you generate data describing the waveform - and this data can then be sent out of the FPGA to a DAC on your board.
The following site gives an example of using the DDS Compiler.
05-28-2020 07:23 PM
thanks a million. That was a great help.
But this approach (using DDS) is technically another solution than AWG, isn’t it? Base on the following discussion: https://www.mwrf.com/technologies/test-measurement/article/21848344/awg-vs-dds-sources-of-contention
It claims that signals with continuous shapes, such as sinewaves, are relatively unaffected by large increments between phase angles. But signals with discontinuous shapes or anomalies or transient characteristics—e.g., fast pulse rise and fall times—can be difficult to create accurately with a DDS.
Is that right?
05-29-2020 04:17 AM
That’s a nice article you’ve found! It gives a clear and accurate comparison of the AWG/ARB and the DDS method of waveform generation.
In short, the Xilinx DDS IP that I mentioned derives all its generated waveforms from a sine wave. This is not a severe limitation of DDS, because Mr. Fourier taught us that any periodic waveform can be represented as a sum of sine and cosine waves (with different frequencies and amplitudes). So, in theory, you could use a bunch of DDS IP and add up their outputs to get any periodic waveform.
However, using a bunch of carefully controlled DDS IP can be kinda complicated and can use up a lot of resources in the FPGA. So, for making waveforms that don’t look much like a sine wave, we use the AWR/ARB approach. The AWR/ARB approach is to generate a bunch of samples on our computer that describe the time evolution of our desired waveform. We then download these samples to the FPGA which stores them in memory. Inside the FPGA is HDL that we wrote to simply read the samples from memory and send the samples out of the FPGA to an external DAC.
With a little more Googling, you might find some HDL that helps you with the AWR/ARB work. However, downloading samples to the FPGA and then using the FPGA to send samples to a DAC is something we usually code ourselves.
On the other hand, the DDS IP is convenient and fast. You don’t need to download samples of a sine wave to the IP. Also, you can command the IP on the fly to change frequency and amplitude of the generated sinusoids. So, creating waveforms like chirps and amplitude-taper sinusoids is a snap. -great for radar and communication work, which is what I do.
-best of luck,
05-29-2020 04:36 AM
Any of your Zynq boards should work nicely. It sounds like what you want to do is to ...
The Zynq should handle writing data to memory easily enough on its own. Xilinx then has a data mover IP which can be used to copy data from memory to your DAC controller. It's called a memory to stream converter, or sometimes an AXIMM2S. The DAC controller itself sort of depends upon what kind of DAC you have, so that's rather application specific.
Beware of memory residing in the Zynq's cache that the MM2S copy IP might not be able to reach. Similarly, beware that the MM2S using physical addressing and many Zynq programs (i.e. Linux) use Virtual addressing.