Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎05-28-2020

How can I implement an AWG (arbitrary waveform generators) on the FPGA

Hi All,

I want to implement an AWG on the FPGA. I don't know however where to start. I have some Xilinx boards at hand like Zybo, ZedBoard and the mighty ZCU102.

Does Xilinx provide an IP for that?

Do I have to code and wirte a costume IP?

The example that I like to implement is as follows, I specify a signal time and amplitude in DDR, AWG reads the values, and pass it to the  DSP.

P.S. 1. Does the flow in my example correct?

P.S. 2. I know there is no ADC/DAC on the above mentioned board, I got stuck still before the DAC.

Any comment is highly appreciated.


All the best


Tags (4)
0 Kudos
6 Replies
Registered: ‎01-22-2015

Hi Jan,


The free IP called the DDS Compiler can be used to generate waveforms.  Details of this IP are given in document, PG141, and an overview is given at the following site.

Specifically, the DDS Compiler will help you generate data describing the waveform - and this data can then be sent out of the FPGA to a DAC on your board.

The following site gives an example of using the DDS Compiler.


Registered: ‎05-28-2020

Hi Mark,


thanks a million. That was a great help. 
But this approach (using DDS) is technically another solution than AWG, isn’t it? Base on the following discussion:

It claims that signals with continuous shapes, such as sinewaves, are relatively unaffected by large increments between phase angles. But signals with discontinuous shapes or anomalies or transient characteristics—e.g., fast pulse rise and fall times—can be difficult to create accurately with a DDS.

Is that right?



0 Kudos
Registered: ‎01-22-2015

That’s a nice article you’ve found!  It gives a clear and accurate comparison of the AWG/ARB and the DDS method of waveform generation. 

In short, the Xilinx DDS IP that I mentioned derives all its generated waveforms from a sine wave.  This is not a severe limitation of DDS, because Mr. Fourier taught us that any periodic waveform can be represented as a sum of sine and cosine waves (with different frequencies and amplitudes).  So, in theory, you could use a bunch of DDS IP and add up their outputs to get any periodic waveform. 

However, using a bunch of carefully controlled DDS IP can be kinda complicated and can use up a lot of resources in the FPGA.  So, for making waveforms that don’t look much like a sine wave, we use the AWR/ARB approach.  The AWR/ARB approach is to generate a bunch of samples on our computer that describe the time evolution of our desired waveform.  We then download these samples to the FPGA which stores them in memory.   Inside the FPGA is HDL that we wrote to simply read the samples from memory and send the samples out of the FPGA to an external DAC.

With a little more Googling, you might find some HDL that helps you with the AWR/ARB work.   However, downloading samples to the FPGA and then using the FPGA to send samples to a DAC is something we usually code ourselves. 

On the other hand, the DDS IP is convenient and fast.  You don’t need to download samples of a sine wave to the IP.  Also, you can command the IP on the fly to change frequency and amplitude of the generated sinusoids.  So, creating waveforms like chirps and amplitude-taper sinusoids is a snap. -great for radar and communication work, which is what I do.

-best of luck,

Registered: ‎05-21-2015


Any of your Zynq boards should work nicely.  It sounds like what you want to do is to ...

  1. Write a waveform of some type into memory
  2. Copy that waveform either once or multiple times to a DAC controller
  3. Send it to the DAC

The Zynq should handle writing data to memory easily enough on its own.  Xilinx then has a data mover IP which can be used to copy data from memory to your DAC controller.  It's called a memory to stream converter, or sometimes an AXIMM2S.  The DAC controller itself sort of depends upon what kind of DAC you have, so that's rather application specific.

Beware of memory residing in the Zynq's cache that the MM2S copy IP might not be able to reach.  Similarly, beware that the MM2S using physical addressing and many Zynq programs (i.e. Linux) use Virtual addressing.


Registered: ‎05-28-2020

Dear Mark and Dan,

I appreciate again your helpful comments. I managed to get what I want but I am still one step behind. I can somehow see that your are pointing to the solution I am looking for, but I have not yet got the clue.


By now, I have used DDS as only a phaser. I wrote my custom Verilog LUT which is 1024 samples of a 15-bit custom waveform. I get the phaser value and map the corresponding custom LUT to the output. I don't have still DAC controller, I am just watching the waveform with the help of ILA.

I want to be able to update my LUT from ARM everytime I want. I see that you said sending data to DAC controller or mentioned Data Mover IP, what is the optimum way to update the LUT? connecting ARM via Data Mover IP to the custom Verilog LUT module and read the stream there and update the 1204 x 15-bit registers?




0 Kudos
Registered: ‎03-27-2014 wrote:

In short, the Xilinx DDS IP that I mentioned derives all its generated waveforms from a sine wave. 
However, using a bunch of carefully controlled DDS IP can be kinda complicated and can use up a lot of resources in the FPGA.  So, for making waveforms that don’t look much l

you are probably better off inquiring about I/Q modulators, how they work and what you can achieve with them.

They're amazingly powerful and very efficient. So efficient you don't even have to bother about resources. You only have two DDSs and two mixers. One DDS describes sine, the other describes cosine. You weight each contribution (I(n) & Q(n)) for each new output sample n.

Simple because you only control I & Q, yet you create advanced waveforms very easily.

If I & Q can only take 0, 1, +1/2 and -1/2, you already have sine, cosine, AM modulation and PM modulation (BPSK, QPSK). If I & Q have arbitrary values over time, you have an total arbitrary waveform. 

You don't even need a CPU or other logic, and should be able to demonstrate the general idea with a small FIFO. After that, you can move to a more complex architecture

Embedded Systems, DSP, cyber