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Explorer
Explorer
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Registered: ‎08-31-2017

How does Vivado implement 26x19 bits MAC via DSP48E1 slice ?

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Hi, dear experts,

I'm thinking of the following problem. Provided that the RTL implementation needs to use a 26x19 bits MAC in 7 series FPGA. As far as I know, the DSP48E1 slice provides a 25x18 multiplier and a 48 bits accumulator as shown in the attached figure. When it comes to implementation in Vivado, how does it synthesized by DSP48E1 slice which one is enough? I'd like to know how Vivado composes the solution by only DSP48E1s or mixed of LUT and DSP48E1s? From the case, it can provide me the guideline how to design the word-length for the MAC operation adequately to optimize the usage of DSP48E1 and performance. 

Thanks 

01172012_fig1.jpg
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Xilinx Employee
Xilinx Employee
362 Views
Registered: ‎09-18-2018

Re: How does Vivado implement 26x19 bits MAC via DSP48E1 slice ?

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Hi @nanson ,

If you require a higher bit operation, you could a cascade operation of the input and partial product from lower slice to upper slice. Details about Cascade implementation are present in UG479,chapter 2, page 30.

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Xilinx Employee
Xilinx Employee
363 Views
Registered: ‎09-18-2018

Re: How does Vivado implement 26x19 bits MAC via DSP48E1 slice ?

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Hi @nanson ,

If you require a higher bit operation, you could a cascade operation of the input and partial product from lower slice to upper slice. Details about Cascade implementation are present in UG479,chapter 2, page 30.

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339 Views
Registered: ‎01-22-2015

Re: How does Vivado implement 26x19 bits MAC via DSP48E1 slice ?

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@nanson 

Understanding how to optimize use of the DSP48 is a good goal. However, synthesis can do this optimization for you.  For example, in a speed grade 3 Kintex-7, I find that Vivado synthesis will infer two DSP48s mixed with LUTs for the 26x19 MACC described by the following VHDL. Further, the inferred circuits will pass timing analysis at clock frequencies above 200MHz.

    signal INA : signed(25 downto 0);    
    signal INB : signed(18 downto 0);     
    signal OUTP : signed(44 downto 0);  
    signal SUMP : signed(95 downto 0);
--
    attribute DONT_TOUCH : string;
    attribute DONT_TOUCH of INA,INB,OUTP,SUMP: signal is "TRUE"; 
--
    P1: process(CLK1)
    begin
        if rising_edge(CLK1) then 
            SUMP <= SUMP + OUTP;
            OUTP <= INA * INB;            
        end if;          
    end process P1; 

Cheers,
Mark