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wardo_82
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Registered: ‎11-17-2020

How should a Simulink model be prepared for FPGA in the loop simulation?

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Hi all, i want to verify a transceiver model i've built using MATLAB through FPGA in the loop co-simulation. The transceiver consists of several blocks with vectors input and output (as it is usual in MATLAB). Is there a correct (better, more convienent) way to connect said blocks to have a better resulting architecture in the FPGA (a Zedboard)?
What i mean by this is that once the blocks are connected, some of the output 50k bits. Should i build a Serial to Parallel block to conect them? or Simulink already takes care of this?
What about input and output ports of the overall model? If simulink is conected through JTAG to the board, should i build a memory block as buffer, previous to the very first block of the transceiver chain, for the input data bits?

Tutorials that cover these topics are also welcome.

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wardo_82
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Registered: ‎11-17-2020

The problem with 50k bit input and output ports lengths is that HDL Generator for Xilinx boards (like the Zedboard) will scalarize it, converting it into 50k separate variables. The project will never compile!
What i ended up doing was designing the algorithms for a bit by bit processing model.

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meherp
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Registered: ‎08-16-2018

Hi @wardo_82 
FPGA-in-the-Loop Simulation is a MATLAB tool. May be, contact MATLAB team for more details. 

We have 'System Generator (sysgen)' tool which does the Hardware co-simulation. 
In Sysgen, the sysgen-blocks between the 'gateway in' and 'gateway out' will be implemented on the hardware (when we use the co-simulation option). 

Gateway-in will be implemented as 'input port' and gateway-out will be implemented as 'output port'. 

Note that, the cosimulation is not supported for all the boards. Once you select the board in SysGen token, then cosimulation option will be enabled, if supported. 



/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
wardo_82
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Registered: ‎11-17-2020

The problem with 50k bit input and output ports lengths is that HDL Generator for Xilinx boards (like the Zedboard) will scalarize it, converting it into 50k separate variables. The project will never compile!
What i ended up doing was designing the algorithms for a bit by bit processing model.

View solution in original post

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