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sheng.liu
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Registered: ‎09-25-2018

How to calculate the output of cascade DSP48E2

Hello Xilinx expert,

We use the DSP48E2 to do multiplication and addition calculation for FIR filter. The target device is xczu15eg-ffvb1156-2-i, the Vivado tool is 2017.4. We use the DSP primitive in Language Templates: Verilog -> Device Primitive Instantiation -> Kintex UltraScale+ -> ARITHMETIC -> DSP -> DSP48E2.

We have two DSP48E2 cascaded, the first DSP48E2 output is the second DSP48E2 input.

The first parameters: ALUMODE = 4'b0000; INMODE = 5'b0_0101; OPMODE = 9'b00_000_01_01.

The second parameters: ALUMODE = 4'b0000; INMODE = 5'b0_0101; OPMODE = 9'b00_001_01_01.

The input data: A = 30bit, B = 18bit, D = 27bit.

The output data: P = 48bit.

Untitled.png

The timing is:

Untitled1.png

We can see that the output P1 has 4 clocks latency relative to the input data. So what is the output value of the second DSP (P2)? Thank you very much.

Best regards,

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nathanx
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Registered: ‎08-01-2007

The Inmode of second DSP48E2 should be "00100", which is (D+A2)*B,  if the INMODE = 5'b0_0101, it's (D+A1)*B. The other settings are correct. Did you set AREG and BREG to 2 in both DSP48E2?

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sheng.liu
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Registered: ‎09-25-2018

Hello @nathanx 

Thank you for your response. Both DSP48E2 has the exactly same configuration. The INMODE is 5'b0_0101 for both DSP48E2. The AREG is 1 and BREG is 2 for both DSP48E2. So what is the value of P2 from the second output?

Best regards,

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sheng.liu
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Registered: ‎09-25-2018

Hello @lvalena

I think you are the Xilinx DSP expert, can you help me to solve this question?

Best regards,

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nathanx
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Registered: ‎08-01-2007

The P2 is determined by the ADreg, Mreg, Dreg, Preg and the other register settings in both DSP48E2. 

Assume the delay from A1, D1, B1 to P1 is 4 cycles, then you need to add 4 regs to A2, D2, B2, which is to get P1 having the same latency with A2, D2, B2.

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sheng.liu
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Registered: ‎09-25-2018

Hello @nathanx 

Thank you for your response. We have the same register setting in both DSP48E2. So the timing of P2 output likes this:

Untitled.png

The P2_0 = (D2_0+A2_0) * B2_0 + P1_0. And it has 5 latency from the A2_0. Am I right? Thank you very much.

Best regards,

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nathanx
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Again, the register setting of your DSP48E2 is not clear.

If you have four regs for A2, D2, B2, then P2 = (D2+A2)*B2 + P1. 

 Yes, the latency is 5 cycles from the A2 to P2. 

The screenshot below can help you to understand the pipeline inside DSP48. The 6th is the P output. The PCIN input is at the 5th cycle.

nathanx_0-1631172151352.png

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sheng.liu
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Registered: ‎09-25-2018

Hello @nathanx ,

It's my fault didn't give the complete parameters of these DSP48E2. For judgment, I compared them and posted them below:

1.png2.png3.png4.png5.png

So except for the input and output data, only the value of OPMODE is a little different because these DSP48E2 is cascaded. The others parameter configurations can also be checked.

The timing of simulation is shown below:

6.png

For the first DSP48E2:

D1 = h’7FFF8A4 = d’-1884

B1 = h’00009 = d’9

P1 = (D1+A1) * B1 = (-1884) * 9 = -16956 = h’FFFFFFFFFFFFBDC4

The simulation shows the result is correct (red). But for the second DSP48E2:

D2 = h’1528 = d’5416

B2 = h’3fe71 = d’-399

P2 = (D2+A2) * B2 + P1 = 5416 * (-399) + (-16956) = (-2177940) = h’FFFFFFFFFFDEC46C

The simulation shows the result is P2 = h’FFFFFFFDDB44 (blue). Can you tell me why it’s different from our calculation? Thank you very much.

Best regards,

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nathanx
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#1, the delay from A1, D1, B1 to P1, it's 4 cycles, the delay from  A1, D1, B1 to P2 is 5 cycles, however, the delay from A2, D2, B2 is 4 cycles, is this intended?

#2,why is the real(p(0) sent to PCIN input of second dsp48E2, the connection from PCOUT to PCIN is dedicated routing, which means you can send p(0) to the PCIN input of second DSP48.

 

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sheng.liu
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It's my clerical error. There is no real_p[0] signal, it is p[0] actually. The P[0] is output from PCOUT of first DSP48E2 and is sent to PCIN of second DSP48E2. I wanna to know for example, P2 = h’FFFFFFFDDB44, how is the output of this calculated? Because no matter how I calculate, I can't get this result.

Best regards,

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nathanx
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Registered: ‎08-01-2007

Assuming in the 6th cycle, P2 is "h’FFFFFFFDDB44", what's the value of P1 in the 5th cycle? And what's the value of A2, D2, B2 in the first cycle? P2 in the 6th cycle equals to (A2+D2)*B2 in the first cycle plus P1 in the 5th cycle.

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