I am a newbie in sysgen field. I am building some simple logical dealing with read & writie to a single port RAM.
I try to export the output of the RAM to workspaces but it seems this method only show the value at every clock cycle according to the exact memory address.
Is there anyway I can check the arbitary content (any memory cell) in that RAM after all operations are completed for the purpose of verifying the logical?
The memory block must be read out one clock at a time by cycling through all the addresses. This represents a real block RAM in the FPGA and can only be accessed this way.