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Visitor jjusto
Visitor
227 Views
Registered: ‎06-03-2019

How to clean all the data stored in an FIR filter generated with IP CoreGen?

Hi, 

MY AIM: Design a FIR filter by using IP CoreGen in ISE 12.1. 

IP I am using: DS534 (datasheet: https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler_ds534.pdf)

ISSUE (this is what I would need): TO CLEAN IN NO MORE THAN 1 CLOCK CYCLE THE INTERNAL STORAGE MEMORY WHERE ALL PREVIOUS SAMPLES WERE STORED (with previous samples I mean: x[n-1], x[n-2], x[n-3] etc).

According to the datasheet given above and some simulations I have done, it's not possible to reset the internal stored samples (from previous clock cycles). Isn't there any way to clean all the past samples stored in ONLY ONE CLOCK CYCLE

NOTE: Yes, I know that it could be possible to send continuosly all zeros in order to clean the internal memory. However, cleaning the filter by sending in zeros needs more than one clock cycle and as I said, I need to clean all the internal memories in only 1 clock cycle.

Have you got any tip of adivce? 

Thank you!

Best regards.

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2 Replies
Moderator
Moderator
185 Views
Registered: ‎08-16-2018

Re: How to clean all the data stored in an FIR filter generated with IP CoreGen?

FIR Compiler v5.0 does not have this feature in it. You need to flush out the data by sending a series of zero. 

 

Also, this feature is included in FIR V7.1

https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_1/pg149-fir-compiler.pdf


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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Scholar dgisselq
Scholar
173 Views
Registered: ‎05-21-2015

Re: How to clean all the data stored in an FIR filter generated with IP CoreGen?

@jjusto,

The fundamental problem here is that it is impossible to clear all memory in one clock cycle given a reset signal.

The solution is to adjust how the filter runs so that it *appears* that the memory has been cleared in a single clock cycle.

In the past, I've done this by keeping track of which memories have "valid" data within them, and then only using those memories to calculate the filter output.  As @meherp noted, the Xilinx FIR cores do not have this capability.  It's rarely needed, hard to build, costs logic, etc.

An alternative you might try would be to use two filters.  You feed the first filter with zeros, and the second filter with your samples.  Once you hit the reset, you start feeding the first filter with samples and return the results based upon that first filter's response.  After a delay equal to the length of the filter, you can switch back to the original filter and start feeding the second filter with zeros again.

It's kludgy, but it would work.

Dan