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Visitor
Visitor
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Registered: ‎02-21-2019

How to config/select FIR filter coefficients set in vivado2018.3 with FIR compiler 7.2?

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I have some trouble in configing the fir coefficients set, if anyone is clear, please help me! Thank you!
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

HI @liuzl ,

The transaction field represents which bits of the m_axis_tdata bus are allocated for the data. In the below pic, the 41 bits of the m_axis_tdata bus carry the actual filter output data while the rest 7 bits are provided to zero pad the data and round it to the next multiple of 8 to be consistent with AXIS protocol.

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Visitor
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Moderator
Moderator
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Registered: ‎08-16-2018
Thanks for adding all the figures nicely.
Can you please add some information on the issue as well?
For example, what are you trying to implement. Which result is unexpected etc. ?

/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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Visitor
Visitor
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Registered: ‎02-21-2019

Thanks for your reply!

The problem has  been solved, and the reason is my wrong use of the lower 31bits data instead of the whole 41bits. 

by the way, the following two different number of bits make me a bit confused. 

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webwxgetmsgimg (1).jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

HI @liuzl ,

The transaction field represents which bits of the m_axis_tdata bus are allocated for the data. In the below pic, the 41 bits of the m_axis_tdata bus carry the actual filter output data while the rest 7 bits are provided to zero pad the data and round it to the next multiple of 8 to be consistent with AXIS protocol.

View solution in original post

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Visitor
Visitor
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Registered: ‎02-21-2019

Thank you very much!

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