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Visitor
Visitor
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Registered: ‎05-20-2020

How to implement 32bit x 32bit multiplier in one clock cycle?

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Hi all,

I would like to implement an AI algorithm where involving a multiplying 32bit by 32bit.  I know there is multiplier IP for this multiplying either by DSP or by LUTs. To make high efficiency, more than 2 or 3-level pipeline should be used which makes high latency, a key drawback in the design.

Is there any other method to implement a 32bit x 32bit multiplier, getting result in one clock cycle while keeping operation clock as high as possible? It is acceptable for slightly higher resource usage if such method exists.

Thanks and best regards,

Jie 

 

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Voyager
Voyager
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Registered: ‎06-20-2012

If one 32bit number is a constant, can I do some optimization?

YES, implement it with LUTs.

The size depends on the number of '1' in the binary encoding.
 
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

The minimum pipeline stage in the Multiplier IP is 1. I think it is tough to achieve such high clock frequencies without pipe lining. The way to check this would be through simulations.

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Visitor
Visitor
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Registered: ‎05-20-2020

Thanks.

If one 32bit number is a constant, can I do some optimization? 

Best,

Jie

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Highlighted
Voyager
Voyager
309 Views
Registered: ‎06-20-2012

If one 32bit number is a constant, can I do some optimization?

YES, implement it with LUTs.

The size depends on the number of '1' in the binary encoding.
 
== If this was helpful, please feel free to give Kudos, and close if it answers your question ==

View solution in original post

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Visitor
Visitor
295 Views
Registered: ‎05-20-2020
Thanks.
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