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As the attached, I need to implement some integral in simulink. I tried, but cannot find any function block for integral in simulink. May you give any suggestion or reference, thanks.

alex9

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11-10-2011 06:59 PM

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Hi,
almost any synchronous block, and that includes the gateway in, needs a setting for the sampling time.
In most cases this is the same or an integer multiple of the Simulink Period set in the System Generator block.
Check all the blocks properties, beginning with the gateway in blocks.
Have a nice simulation
Eilert

eilert

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11-16-2011 01:48 AM

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eilert

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11-10-2011 10:25 PM

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Hi,

in the simulink/Continuous library you find a number of Integrator blocks with different special abilities.

But this is a Xilinx related forum, so is this question in any way related to FPGAs or the System Generator tool??

Have a nice simulation

Eilert

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alex9

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11-14-2011 12:28 AM

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I am using SP605 board and sysgen.

There are some Integrator blocks, but they are not xilinx blockset, or I missed any of them.

Any suggestion, thanks.

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eilert

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11-14-2011 01:08 AM

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Hi,

for that you need to understand what an integration is. It's a sum over time.

A simple Accumulator block from the xilinx blockset can do an integration.

It has by default a synchronous reset and the feedback can be scaled down too.

All you need to provide is a signal that determines the time over that you want to integrate your data.

Another approach would be to use a lowpass FIR. But you need a special set of coefficients and the hardware will use much more ressources.

Have a nice synthesis.

Eilert

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alex9

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11-14-2011 06:59 PM

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So for example the waveform has 1024 points, the time inteval is 10ns,

the integration= sum(W1+W2+...+W1024)x10ns

Is this correct, thanks.

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alex9

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11-15-2011 12:42 AM

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I am trying to make the integrator as the attached screen.

Any suggestion, thanks.

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Hi,
yes, that's basically it.
Of course this way you get the integral of the stairway-shaped sampled signal to be exact.
But 10ns/1024 is quite close to an infinitesimal zero, so it will be a good approximation.
Also, from a technical point of view, you may be able to optimize away the multiplier.
Multiplication/division by a 2^N value is a simple shift (or reassignment of the numerical weight).
So, if you find a 2^N representation of 10e-9 that has sufficient accuracy, the multiplier vanishes or can be replaced by one or two adders for the shifted result.
Furthermore it may be that the time interval can be canceled out in the further processing of the data, so no multiplication is needed at all.
Remember, that you need some circuit that resets the Accumulator after 1024 samples, so the integration can start over again. or add a 1024 word shift register and subtractor to get a floating integral .
There are so much possibilities. But it depends on your application.
Have a nice simulation
Eilert

eilert

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11-15-2011 07:38 AM

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alex9

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11-15-2011 08:23 PM

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As the attached simulink file link, I tried to make a simulation.

http://www.fileserve.com/file/pMJXruR/integration.mdl

The sampling time interval is 10ns, and the total time duration is 10us. So there are 1000 data points totally.

But it give error when run up as attached, it seems the time setting is not correct. I checked several time, but not sure where got problem.

Any suggestion, thanks.

Highlighted
Hi,
almost any synchronous block, and that includes the gateway in, needs a setting for the sampling time.
In most cases this is the same or an integer multiple of the Simulink Period set in the System Generator block.
Check all the blocks properties, beginning with the gateway in blocks.
Have a nice simulation
Eilert

eilert

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11-16-2011 01:48 AM

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alex9

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11-20-2011 08:12 PM

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After the integration, a square root is needed. But the output of the integration is fixed point, the input of the square root request floating point.

Any suggestion, thanks.

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eilert

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11-21-2011 02:53 AM

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Hi,

so the sqrt block seems not to be part of the xilinx bloxk set.

In that case you have to use a gateway out block between them.

Have a nice simulation

Eilert

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alex9

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11-22-2011 12:29 AM

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The square root is counteracted by a square, so no worry about this part.

Now I implement a divider, but as the attached, it will take quite long time when try divide by 2.

Is there any way to manage it, I am a newbie, thanks.

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eilert

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11-22-2011 04:12 AM

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Hi,

as you can see from the z⁻¹⁰⁰ you get a delay of 100 clock cycles.

Of course a division by two (or any 2^N value) can be made immediately. It's a simple shift to the right by N.

You can use the reinterpret block for that.

e.g. UFix_16_8 reinterpreted to UFix_16_9 is a nice division by two that costs neither time nor ressources.

The cordic divider is more of inderest for divisions by very complex numbers like 1.7432412314245 or such.

Have a nice simulation

Eilert

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alex9

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11-22-2011 06:51 PM

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In the real case, it will be a bit complex number. And quite difficult to tell which is the number I want.

The sequence is like this, do integration for 1024 points(one wave), then make a divider for the integration of the 1024 points and get one number.

The problem is the integration give result for every point just like a shift window, It will keep feeding the divider, not as expected, only feed the divider at the wave end(the 1024th point), and it take 100 clock to finish, so may miss the wave end and not sure which point the divide result is.

Any suggestion, thanks.

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eilert

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11-22-2011 10:54 PM

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Hi,

so the 2 thing can be ruled out. Would have been too nice this easy way.

Instead you are facing now the wonderful world of system design.

Some rules of thumb to ease your live.

1) Latency is unavoidable, don't fight it.

2) Make pipelining your friend.

3) Learn about system controll (e.g. FSMs)

Just a simple example with your design:

You can make the integration floating, like already described. First meaningful results can be expected after 1024 clocks.

The cordic divider is pipelined too, so after 100 clocks the results are coming out on each clock too.

Say you start both at once. Then you get the first usable result after 1124 clocks.

So with a simple counter that stops at 1123 and generates some EndCount signal you can generate a Valid signal for your results.

These results wil have a fixed delay, but what's the problem. An analog solution would have a delay too (commonly known as phase shift) and there the phase shift normally is not constunt but a function of the frequency too. So you already have some improvement. :-)

But even if you don't have a floating integrator or the divider isn't pipelined.

In that case you need some FSM to controll the data transfer between your function blocks.

The bad news: This makes some work.

The good news: Now you can work on improvements too!

Say, if you look at the datarates in your design and compare them to the FPGAs clock rate.

There may be some headroom, use that. e.g. if your divider needs 100 Clocks but the datarate coming from the Integrator is just 1MSPS then you can run the divider with 100MHZ, and so the felt delay wil be just 1 tick of the 1MSPS datarate.

Also, there may be other Divider cores that are faster anyway. Cording saves you ressources, at the cost of latency.

If yor divisor is known and (finally) constant, you can also create the inverse and multiply it with your integrator results. Multipliers using DSP48-hardmacros are quite fast.

So there's a lot you can do, but it needs careful engineering.

Have a nice simulation

Eilert

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alex9

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11-24-2011 01:53 AM

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Your answers really show the direction of the work will go.

I tried to implement them and read some reference, but still met some difficulty.

For the first method, the divider module not have an enable input. What I can think of is using a down sample 1024 for divider, but it will also slow down the output of the divider. If using a 1024 delay, the divider is still keep runnning all the time. Is there a package with enable function can pack the divider in.

For the second method, I tried some simple sample of FSM. But not sure how to link FSM to enable the divider.

Or is there any sample of implemention. Any suggestion, thanks.

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eilert

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11-24-2011 03:04 AM

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Hi,

many xilinx blockset elements can have enables and synchronous resets as extra inputs.

When you open the blocks configuration dialog you may find the checkerboxes there.

Once selected, the extra input appears at the symbol and can be used by the controll logic (e.g. some FSM).

Is there some special block that's giving problems? Please tell in detail.

Have a nice simulation

Eilert

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The cordic divider as attached seems not have the enable function. Is there any other way to implement this function. Thanks.

alex9

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11-24-2011 07:33 PM - edited 11-24-2011 07:33 PM

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eilert

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11-24-2011 11:21 PM

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Hi,

that's right, because the Cordic Divider is no basiuc element, but a reference application.

You could use CORDIC 4.0 to create your own cordic divider with enable.

But more straightforward would be the use of the Divider Generator 3.0, which also can be implemented with enable and sync. reset.

Have a nice simulation

Eilert

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alex9

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11-27-2011 07:29 PM

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Hi,

The Cordic 4.0 has some functions, but no divider inside.

Also, the Divider Generator 3.0 is for integer, some of my number may < 1.

Any suggestion, thanks.

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eilert

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11-27-2011 11:34 PM

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Hi,

the cordic 4.0 is just a building block, and to do a division with it needs some knowledge on how CORDIC works.

A point to start:

http://en.wikipedia.org/wiki/CORDIC

Binary numbers have no idea wether they are integer or fixed point.

There is just no representation of a decimal point, it's all happening in the designers mind.

If you are multiplying 010/010 you expect the result to be 000001

You can do the same with 0.10 / 0.10 =000001

If you have the same number of fractional bits on your operands, your result will be integer again.

Funny point of this example, it looks the same for decimal and binary. :-)

You can do the same for multiplication, only that the fractional bits add up in the result.

e.g.: 010*010=00100 and 0.10 * 0.10 = 00.0100

So, don't trust point and click interfaces blindfolded.

Use your own mind and understand what's really happening in your design.

Have a nice simulation

Eilert