12-13-2017 12:21 PM
do you know how to program a moving average filter in FPGA using blockset of Xilinx in Simulink? The FPGA frequency is 100MHz and ADC frequency is 10MHz. I want to program the moving average filter using blockset of Xilinx in Simulink. It is located after ADC.
I have tried but failed. If anyone knows, i will really appreciate for it. Thanks a lot in advance.
12-13-2017 07:36 PM
12-13-2017 09:28 PM
12-14-2017 10:41 AM
12-14-2017 10:43 AM
12-14-2017 05:55 PM
Not sure I understand. If you implement a moving average filter properly, sending a zero input into the filter will (eventually) result in a zero output. What constant error are you talking about?
12-15-2017 06:05 AM
There are a lot of ways to implement a moving average filter in Sysgen.
I recommend the following way which has a periodic reset and as such removes continues errors:
Use a Dual Port RAM with input A for write with write enable at the rate of your desired signal.
Use Port B for read at the your FPGA system rate which should be higher than the number of points in the Dual port RAM.
start the read control after writing a new sample into the DUAL Port RAM. You can easily accumaulate the values using an addsub with 1 reguster feedback. use that register to reset the "accumulator" you build that way then divide by the number if samples you expect to get the result. Powers of 2 are best here as that makes best use of the ressources and your divider becomes a simply shift operation.
using this method you can use the write enable of the DUAL PORT RAM as a clock enable and your filter speed i variable (as long as your read rate is at least number of samples faster than your write)
This filter can easily be used for multiple inputs and outputs with a bit of logic around it.
If you have a fixed sample rate you can simply build and accumulator at the sameple rate and subtract the input signal delayed by the number of samples.
01-22-2018 10:40 AM
before i have programmed moving average filter sucessfully. Thanks for your advice!
Now i have one more question, do you know how to program a simple low pass filter in FPGA using blockset of Xilinx in Simulink? Because in the experiment there are so many noise with high frequency.
I have found that the block "FIR Compiler 5.0" maybe work, but i don't know how to set up such as the cutoff frequency is 10kHz. Do you know how to use this block or do you have any other good idea to program a simple low pass filter in FPGA?
Thanks a lot.
05-18-2018 06:44 AM
A good reference for building a lowpass filter in an FPGA? How about this one? It discusses the basics of filtering, how to go about generating taps, and even shows how to implement a basic FIR filter. Depending upon your application, you might find this alternate implementation better for your needs. There's also a really cheap, really simple, single pole IIR filtering implementation that works as a crude lowpass filter. Sometimes that meets my requirements--particularly when I'm building control systems.
You'll find those two articles are part of a longer series on digital signal processing within FPGAs. If you are interested, you can find links to all of the DSP related articles here.
05-18-2018 06:59 AM