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Visitor linhtt
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Registered: ‎06-30-2019

How to run DPD in TDD mode?

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Hi all,

My concern is about how to run DPD Ipcore in TDD mode. 

In TDD mode, each subframe will contains downlink or uplink data and DPD algorithm is only applied for downlink data. So in DPD Ipcore, how to detect downlink or uplink data in input stream data for applying DPD algorithm?

Please help me to clarify clearly.

Many thanks.

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Observer poseidonj
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Registered: ‎10-21-2014

Re: How to run DPD in TDD mode?

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Followings are based on my experience:

Well, let's assume that a mobile data is in "ddduu" format for TDD mode, and of cause "d" stands for downlink. First of all, you have to understand that the High power Amplifier in the downlink side amplifies only the downlink signal by using "ddd__" window signal provided by a system. Then, the amplified signal "DDD__" goes to antenna modules and also feeds back to DPD engine.

Therefore, DPD engine receives "ddduu" as the downlink and "DDD__" as the feedback, and uses the two signals to correct the distortion induced by DAC/AMP/Analog module in the system. To do that, at the very first beginning, DPD tries to align the two signals in the time domain to compare and to run the algorithm. The SCA block in DPD aligns the two signals within "DDD" window.

Furthermore, in the actual DPD application, the system feeds "ddd__" as a downlink signal to DPD instead of "ddduu" to reduce uncertainties caused by DPD or the system.

 

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Observer poseidonj
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Registered: ‎10-21-2014

Re: How to run DPD in TDD mode?

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Followings are based on my experience:

Well, let's assume that a mobile data is in "ddduu" format for TDD mode, and of cause "d" stands for downlink. First of all, you have to understand that the High power Amplifier in the downlink side amplifies only the downlink signal by using "ddd__" window signal provided by a system. Then, the amplified signal "DDD__" goes to antenna modules and also feeds back to DPD engine.

Therefore, DPD engine receives "ddduu" as the downlink and "DDD__" as the feedback, and uses the two signals to correct the distortion induced by DAC/AMP/Analog module in the system. To do that, at the very first beginning, DPD tries to align the two signals in the time domain to compare and to run the algorithm. The SCA block in DPD aligns the two signals within "DDD" window.

Furthermore, in the actual DPD application, the system feeds "ddd__" as a downlink signal to DPD instead of "ddduu" to reduce uncertainties caused by DPD or the system.

 

Visitor linhtt
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Registered: ‎06-30-2019

Re: How to run DPD in TDD mode?

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Many thanks for your reply.

But the key point is " the system feeds "ddd__" as a downlink signal to DPD instead of "ddduu"" in your comment?

How does the system feeds "ddd___" as a downlink signal to DPD instead of "ddduu"" because in reality, "ddduu" is transmitted on system? On the other hand, what does DPD based on to detect "ddd___" signal?

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Observer poseidonj
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Registered: ‎10-21-2014

Re: How to run DPD in TDD mode?

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What you misunderstand is that the "ddduu" is an air signal that flows in the air for TDD wireless services. The RF amplification system such as DAS that implements DPD uses a frame sync signal coming from BaseStation to separate the downlink and uplink signal. It means that the system handles "ddd__" at the downlink side and "___uu" at the uplink side.

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Visitor linhtt
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Registered: ‎06-30-2019

Re: How to run DPD in TDD mode?

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I understand what you mentioned. 

But my question is about DPD actions in TDD mode. 

For example, in the downlink phase, DPD acts properly, of cource. But in the uplink phase, Does DPD acts or not? If the answer is YES, DPD core will push out continuous warning because input and feedback signal power is very, very low. If the answer is NO, Why does DPD know it is in uplink phase? What port of DPD Core does the "frame sync signal" that you mentioned connect to?

Thank you so much.

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Observer poseidonj
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Registered: ‎10-21-2014

Re: How to run DPD in TDD mode?

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Firstly, DPD doesn't know whether the input (downlink) signal is for downlink or uplink. The downlink signal feeding to DPD has RF power in the downlink timeslot whereas NO power in the uplink timeslot. Therefore DPD aligns downlink/feedback signal within the downlink timeslot because nothings are observed in the uplink timeslot. The SCA(Sample Capture Acceptance) block in DPD does that. Please see the user manual for more details. And if you want to know more about how the SCA works, contact Xilinx.

Furthermore, a user can assign a specific point to start measurement and alignment, by setting followings:

  - Set CAPTUREMODE = 1

  - Set CAPTUREDELAY to the user specified delay from FrameSync signal.

  - Connects the Frame Sync signal to the CAPTURE_SYNC port of DPD.

 

However, as I know, the CAPTURE_SYNC port is not available since DPDv7 because the SCA detects the best position for predistortion algorithm.

Correction on Oct/11/2019:

CAPTURE_SYNC port has been moved to s_axis_din_tuser bus since DPDv7.

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Visitor linhtt
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Registered: ‎06-30-2019

Re: How to run DPD in TDD mode?

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Many thanks. I totally understand.

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