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misiewl
Visitor
Visitor
4,006 Views
Registered: ‎01-06-2009

Hw-Cosimulation Time

I have a system which I am running as a hardware cosimulation component. That system needs to run at 32 MHz minimum clock speed. I also have a system whhich communicates with the FPGA using shared memory. My understanding is that the Simulink period needs to be at least 1/32MHz for the simulation to run. The problem is that with that high of a frequency the simulation runs extremely slow. My question is: Is there any other way to communicated with the shared memory on the board except the hardware cosimulation? If yes, the help would be much appreciated. Also, if there isn't, how can I speed up the simulation?

 

Thanks in advance. 

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ywu
Xilinx Employee
Xilinx Employee
3,973 Views
Registered: ‎11-28-2007

Shared memory is actually your friend for speeding up hwcosim. Usually it's the gateways between the SW and HW that slowe down the simulation. If you have many gateways in your hwcosim model, you should try to reduce that as much as y ou can.

 

Cheers,

Jim

 

Message Edited by jimwu on 02-16-2009 06:58 PM
Cheers,
Jim
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benchan
Explorer
Explorer
3,525 Views
Registered: ‎09-28-2007

You may find the following application note useful in understanding how to speed up your simulation.

 

XAPP1031: Decreasing Simulation Runtimes with System Generator for DSP Hardware Co-Simulation

 

http://www.xilinx.com/support/documentation/application_notes/xapp1031.pdf

 

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