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Sam23
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Registered: ‎02-11-2021

IIR filter timing issues

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Hi guys, I am currently building a IIR Low Pass Filter by using an FSMD design. I designed the ASM chart and coded the FSMD into Vivado to test is out. Initially I simulated the system by using behavioural simulation, and everything seemed to be working properly and as expected. However I then tried to move on to Post-Implementation Simulation before programming the FPGA and the output of the simulation was completely different and wrong.

This is the Behavioural Simulation output:

behavtop.PNG

This is the Post-Implementation Simulation output:

posttop.PNG

Once I saw this issue, I thought maybe the shifting operations in my code are not being executed in order. Hence I split up my Functional Block into more states, however the result was also incorrect (and more difficult to understand what is happening).

Note that Post Synthesis Functional Simulation works, however the wrong output is generated for Post Synthesis Timing Simulation.

I think(well it has to be) a timing or synchronisation issue, however after many trails to debug the issue I didn't succeed to locate the bug. Am I doing a  silly mistake somewhere in my code or is there something fundamentally wrong that I am overlooking.

Thanks, for the help I highly appreciate it.

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drjohnsmith
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Registered: ‎07-09-2009

Well done you for simulating,

A differ3ence between simulation pre and post synthesis is normally down to :

a) sensitivity list errors, ( look at the warnings )

b) latches ( look at the warnings ) 

BTW:

A touch stone I use, is if people are using this sort of code 

mclk_fsmd'event and mclk_fsmd = '1'

instead of

rising_edge( mclk_fsmd )

 

I recommend this book

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

you also dont need to include the 

"component" in the test bench,

use the entity work.<entity_name> format

 

My guess is you have made latches as you are using a two process state machine.

    use a one process state machine is very recommended. 

 

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Well done you for simulating,

A differ3ence between simulation pre and post synthesis is normally down to :

a) sensitivity list errors, ( look at the warnings )

b) latches ( look at the warnings ) 

BTW:

A touch stone I use, is if people are using this sort of code 

mclk_fsmd'event and mclk_fsmd = '1'

instead of

rising_edge( mclk_fsmd )

 

I recommend this book

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

you also dont need to include the 

"component" in the test bench,

use the entity work.<entity_name> format

 

My guess is you have made latches as you are using a two process state machine.

    use a one process state machine is very recommended. 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Sam23
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Registered: ‎02-11-2021

@drjohnsmith  thanks for the help  

Do you have an idea of how I can solve the following warning:

  • [Synth 8-327] inferring latch for variable 'y_n1_next_reg'

Since I would like to keep two process such that the result of the FSMD is registered and latched.

Thanks

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Sam23
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Registered: ‎02-11-2021

@drjohnsmith 

Also when I updated my sensitivity lists such that the warnings regarding them were gone, the logic of the FSMD is not working correctly, in fact it is working like the post implementation simulation:

Sam23_0-1613045984098.png

I can't understand why the 'shift_load' state is not working as desired, that is sequentially.

Thanks

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bruce_karaffa
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Registered: ‎06-21-2017

@drjohnsmith already gave a hint as to avoiding latches in a state machine.  Use a one process state machine instead of a two or three process state machine.  That is, put the output signals into the clocked process with the state assignment.  If all of your signals are clocked, you should not get a latch.  Also, do you have timing constraints?  Does the design meet these constraints?  What does your clocking structure look like?

drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Latches are a problem,

  always look at warnigns,

 

Latches are formed when there is no state in the code for the output,

   Also ,

the two process state machine does not make a latch and a register,

    its all a single register.

 

Have a look a the book,

   dump the two process machine ,and see what you get.

 

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drjohnsmith
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Registered: ‎07-09-2009

thats good now that the sensitivity list error is gone that the pre and post simulate the same.

Now get rid of the latches and your onto a winner

 

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Sam23
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Registered: ‎02-11-2021

@drjohnsmith  This is the result that I am obtaining when I removed the latches, I changed some of the code that I sent at 5.13AM :

Result of Behavioural Simulation:

Sam23_1-1613051952799.png

 

Result for post-synthesis:

Sam23_0-1613051871756.png

 

Seems as if there was no difference for the behavioural simulation, however now the post synthesis is not working completely.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

a) read the FPGA book I sent link to

b) go for a one process state machine

c) sort out your libraries, why do yo need these three ?

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;

 

never use a none IEEE library ,

   you will see that there are many potential problems mixing libraries from different sources.

   Its in the FPAG book 

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html

https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

 

 

 

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