I've got a problem with simulating Xilinx Fast Fourier Transform v9.1 IP using VCS. There is no data on the output AXIS interface. It works correctly with Vivado simulator IP. I have attached IP and Vivado native testbench.
VCS version Q-2020.03 Vivado version 2018.3
According to information in the release notes for Vivado 2018.3 (UG973 December 14, 2018) VCS N-2017.12-SP2 and above are supported.