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Registered: ‎11-14-2017

ISIM : Output of a FIR compiler core is always stuck at 0



I am getting stone-walled by this ISIM bug when I am trying to simulate my FIR compiler IP core. I get this message on the ISIM simulation console at the beginning of time:


at 0 ps, Instance /tb_aeye_ladar/uut/in_fifo_ctrl_inst/i_near_iir_inst/sos1_inst/sos1_reverse_fir_inst/U0/g_mac/mac/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

at 0 ps, Instance /tb_aeye_ladar/uut/in_fifo_ctrl_inst/i_near_iir_inst/sos2_inst/sos2_reverse_fir_inst/U0/g_mac/mac/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0


As you can see, I have two different implementations of a FIR filter and both of them are getting with the same message.


Although, it is a warning, what I see in my simulation is that the FIR filter output is always stuck at ‘0’ and never changes. This is the main issue and I can’t move forward or simulate my design any further because of this. Please see the bus reverse_fir_out in the waveform below, which shows the signal not changing in a run of over 20 us. Interestingly, the output is stuck at ‘0’ from the get go.


If I know where the problem is, then I can probably fix it. Unfortunately, the location it is referring to is a Xilinx VHDL model for the FIR filter and I am not able to access it. File "N:/P.20131013/rtf/vhdl/src/XilinxCoreLib/fir_compiler_v5_0_mac_fir.vhd" Line 3318


I have regenerated my FIR filter cores a couple of times and that did not help at all. I have searched the Xilinx website for this particular error, but didn’t see anything relevant. 


I have another instance of a FIR filter with different coefficients and order and that simulates without any issues.


Any thoughts?

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4 Replies
Registered: ‎02-24-2014

What's happening with the FIR reset during this simulation?  from the error message, it sounds like it's converting 'X' into 0, and you probably have some 'X' state persisting in an accumulator inside the core.    Try making sure that your reset is applied starting at time zero, and is only released after 20 clock cycles.

Don't forget to close a thread when possible by accepting a post as a solution.
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Registered: ‎05-21-2015

Why not use an open FIR core that you can debug?  You can find a variety of them in this repostory on Github.  Most (all?) of them have been discussed and developed on, so you should be able to understand how they work from there.  Further, since they are open source, you can also simulate them using Verilator (if your design is in Verilog)



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Xilinx Employee
Xilinx Employee
Registered: ‎05-06-2008

Hello Nreddy,

Did this issue get resolved?

If so, can you mark the correct response as an accepted solution?

If you have more questions, please let me know.

Thank you,

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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

This is a bug in ISE Simulator which is affecting the "drive_zeros" procedure in the testbench. Modifying the line 266 in this procedure from: drive_data((others => '0'), samples); to drive_data((others => '0')); allows the simulation to run. Modelsim does not see this issue and ran successfully.

Thanks and Regards
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