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Registered: ‎05-17-2018

Implementation of long delay in sysgen using xilinx blocks

I want to delay a sinusoidal waveform by 0.005sec
My Fpga is clocked at 25ns
The delay block of xilinx has a limitation of up to what latancy delay we can put.
To get 0.005 second delay i have to use a latancy of (0.005/25ns =200000) which is quite a big latancy and thus cannot be kept for generation to build model.
So in delay help section it is said we can use different approach which is based on gailos field theroy using register LFSR
Can any one explain with this example of 0.005sec delay
Step by step procedure for this delay model
If possible email me the block that you have design for my application (0.005sec delay-which delays a sine wave input continuesly) (mandarkomarpant@gmail.com)
It will be helpful for many
Thanking you in advance
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Registered: ‎08-01-2007

Re: Implementation of long delay in sysgen using xilinx blocks

Using LFSR or block ram to build this delay.

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