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Registered: ‎05-21-2013

Implementing DDC on CPLDs



The have an ADC sampling at 37.4MSps and I want to fed this data into a DSP for real-time baseband processing. However, I need an interface between the ADC and DSP to digitally down converter the bandwidth of interest (Fs/4 = 9.35MHz) to baseband, so the DSP processing load is reduced. I'll use a NCO generating a signal at Fs/4 - 9.35MHz, also generating I and Q. This shouldn't need too many resources.


I'm looking for a low cost solution (rather than using FPGA) and I am wondering if a DDC can easily be implemented by a CPLD? There doesn't seem to be many resources online for this. 


Kindest regards,



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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

Re: Implementing DDC on CPLDs

DDC core is not supported for CPLD.
Thanks and Regards
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