Implementing Low-Frequency Phase Locked Loop in System Generator
Hello Xilinx Community,
I am trying to implement an all-digital phase-locked loop in system generator that can lock onto a 10 kHz signal. I've implemented a standard-flip flop based phase frequency detector (using registers and counters), I'm using the DDS compiler as a numerically controlled oscillator, and I build a PI filter using adders and multipliers. I've tested each of my blocks independently and they are working. However, when I combine them to make the PLL, I'm not able to maintain a lock. Does anyone have experience designing a PLL in XSG that could provide ideas on how to troubleshoot this?
While its not XSG, this article offers Verilog source code for a PLL built from logic. Debugging is done via extended simulation with Verilator, and the debugging code is discussed (and included) as well.