Import EDIF into system Generator?

[jmonteiro-dme]

Hello,

1) Is it possible to import an EDIF (or NGC) file into system generator as a black box, having access only to its inputs and outputs?

2) As far from what Ihave understood from manuals, black boxes in system generator need vhd code. System generator is not able to read output and input interface ports from the edif?

3) Does ISE (ProjNav) allows us to export a vhd project into a readable format into matlab/system generator?

Best,

JM

[criley · Accepted solution]

Hi Jim,

You'll want to use the Black Box Block for importing EDIF (or NGC) files into your System Generator design.  You will however need to have a wrapper file for the netlist though which you can create manually or if you are unsure of the I/O's for the netlist you can "netgen" command line which generates VHDL or Verilog structural model which you can then take the I/O declaration from.

Syntax for NetGen Functional Simulation

netgen -ofmt [verilog | vhdl] [options] input_file[.ngd | ngc]

Note: if you have an EDIF you can run "edif2ngc" to convert it to an ngc to use for netgen. 

ISE (ProjNav) doesn't have the ability to create a block build from the the ISE project so the best way would be to run through synthesis on the iSE project and then use another Black Box Block in SysGen to import the netlist using the appropriate wrapper file.

-Chris

[jmonteiro-dme]

Many thanx for your clear answer Chris, no doubts now :)

Best,

JM

[simopal6]

I have one question: are the NGC files created by "Synthesize" and "Implement" different?

Thank you!

[jmonteiro-dme]

Yes, synthesis creates the .ngc file, implementation creates files related to place and route of the design in your specific FPGA. The following might help:

http://www.xilinx.com/itp/xilinx8/help/iseguide/html/ise_using_xst_for_synthesis.htm

Best,

JM

[vikasparashar]

hi,

 I am trying to import a edif into a system generator BB.. I am doing it as you have already suggested but its not working.

It seems as if netlist is not tied up with BB.. In the config M file i have added my edif as per the format suggested ..

I have setup the simulation mode of BB as ise simulator ..

BB is behaving as if it is dead and sysgen is not reporting any error..

Plz. suggest what may be the probable issues?

thnx..

viaks

[ywu]

You need add the simulation model (vhdl or Verilog) to the configuration m file as well.

[vikasparashar]

thnx, issue resolved.

[vikasparashar]

Is such a blackbox of sysgen  synthsizable which is having a edif netlist into it..?

what i think is ..that blackbox is working with a postsynthesis .vhd file of the netlist so is it possible to synthesize a model which have such a BB....?

thnx ..

vikas