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bhanu27
Contributor
Contributor
579 Views
Registered: ‎05-10-2019

Instantiate CORDIC block in RTL

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Hi All,

 

I am using Xilinx CORDIC IP in block diagram.

I wish to instantiate it directly in RTL rather than in block diagram.

In the IP sources, i donot see any verilog or VHDL template file. 

Any ideas where I can find the instantiation template for this block

 

 

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meherp
Moderator
Moderator
515 Views
Registered: ‎08-16-2018

Hi @bhanu27 

After instantiating the IP, you can see the template in IP resources as shown in below screenshot, 

Screenshot_3.png


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

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meherp
Moderator
Moderator
516 Views
Registered: ‎08-16-2018

Hi @bhanu27 

After instantiating the IP, you can see the template in IP resources as shown in below screenshot, 

Screenshot_3.png


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

View solution in original post