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Explorer
Explorer
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Registered: ‎07-03-2014

Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

Hi!

My design on Spartan 3 has been working perfectly for past 8 years; some weeks ago, one of our costumers asked us to improve output filtering in order to save money in physical filters.

The output stage of my design is a interpolation filter for a OFDM signal (bandwith = 4MHz) that upsamples from Fs=10MHz to Fs=50MHz; after upsampling, the I/Q data samples go to the DAC. This filter is implemented using FIR Compiler 5.0, with the following configuration:

Options.png

The filter is instantiated twice, one for I samples and one for Q samples, instead of increasing number of channels to 2. Besides, the implementation is "Distributed Arithmetic", and that is the key: if I change to "Systolic Multiply Accumulate", the design won't work anymore.

After changing the implementation to use DSPs, I can see my output signal completely distorted in the Spectrum Analyzer: it has 5 times the baseband bandwidth, so I can see 40MHz of bandwidth (4MHz baseband I/Q x 5 upsampling factor) in the analyzer. It looks like the core is not filtering in "Systolic Multiply Accumulate" mode. However, if I simulate the design and process the filtered data in Matlab, it looks like the simulated output data is correct.

I tried a trick that didn't work: I set the FIR Compiler core to "Single Rate" and then I add null samples before entering the filter (i.e., the new input sampling frequency is 50MHz). The result is that the filter uses 4 times more DSP than if I set "Interpolation" type.

Any ideas of what's happening?

King regards!

Options.png
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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

As it works in simulation, A guess, Are you constrained and does your design meet timing ?

Also, in case, ISE does not work under windows 10,
so if you have W10, you need W7 or linux,
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Registered: ‎07-03-2014

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

My design doesn't meet timing (timing score about 6500) when using distributed arithmetic filtering, but it does when using systolic multiply accumulate. I didn't change the constraints after changing between both... Is there any special constraint I must use or something?

As for Windows 10, I know ISE 14.7 doesn't support Windows 10, but with the SmartHeap patch everything works fine. Anyway, the design works with the distributed arithmetic filter, so I think W10 is nothing to do.

Thanks for your answer!

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

In my experience, ISE under windows 10, is un reliable, seems to work but does not ..
And yes over the years I have followed and tried all the patches and plugs that come to mind.
I now run W7 on my own VM as a reliable way of getting results for my clients that want CPLD's

If I understand, you have a design that works in simulation and fails in the device ?
That smells of timing problems,

Just because one design that fails timing seems to work on one chip, does not a design make.

I'd strongly suggest fix the known problems first as a way forward.


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Registered: ‎07-03-2014

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work


@drjohnsmith wrote:
In my experience, ISE under windows 10, is un reliable, seems to work but does not ..
And yes over the years I have followed and tried all the patches and plugs that come to mind.
I now run W7 on my own VM as a reliable way of getting results for my clients that want CPLD's

I'll try on my Windows 7 VM and will share the results in this thread.

 


If I understand, you have a design that works in simulation and fails in the device ?
That smells of timing problems,

Just because one design that fails timing seems to work on one chip, does not a design make.

I'd strongly suggest fix the known problems first as a way forward.

It is the other way round... The design that doesn't meet timing is the one that implements the distributed arithmetic filter, which has been working 24h/7d on several costumers for 8 years. The design that does meet timing is the one that implements the systolic filter, which is the design that doesn't work at all.

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Teacher
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Registered: ‎07-09-2009

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

personally, if you have a W7 VM, I would only run ISE in that

Did the design that works with the customer originally fail timing or is it just the resent version of ISE that's showing this ?

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Registered: ‎07-03-2014

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work


@drjohnsmith wrote:

Did the design that works with the customer originally fail timing or is it just the resent version of ISE that's showing this ?

I'm pretty sure that the design released on 2012 achieved timing closure with ISE 14.1. I migrated the original design to 14.7 (with distributed arithmetic filter), updated all cores to the latest version (microblaze, fifos, filters and so on) and after that, it failed timing.

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Teacher
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Registered: ‎07-09-2009

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work

I cant remember the spartan timings being updated between 14.1 and 14.7, but they might have been, xilinx do do that,

This is a strange one, would it be worth while getting the 14.1 you originally made the design with, getting a new checkout of the archived project and checking it all worked ,

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Scholar
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Registered: ‎06-20-2017

Re: Interpolation FIR filter with FIR_Compiler 5.0 doesn't work


@alexmoya wrote:

I'm pretty sure that the design released on 2012 achieved timing closure with ISE 14.1. I migrated the original design to 14.7 (with distributed arithmetic filter), updated all cores to the latest version (microblaze, fifos, filters and so on) and after that, it failed timing.


Try smartxplorer xilinx and/or try changing your starting cost table. 


@alexmoya wrote:

After changing the implementation to use DSPs, I can see my output signal completely distorted in the Spectrum Analyzer: it has 5 times the baseband bandwidth, so I can see 40MHz of bandwidth (4MHz baseband I/Q x 5 upsampling factor) in the analyzer.


Also simulate your filter with impulse response, take FFT of response in matlab.  Is it still 5 times what you expect?  If so, it is consistent with your external measurements.  If not, something else is going on.

Also check sizing of word size with full step response.


@alexmoya wrote:

I tried a trick that didn't work: I set the FIR Compiler core to "Single Rate" and then I add null samples before entering the filter (i.e., the new input sampling frequency is 50MHz). The result is that the filter uses 4 times more DSP than if I set "Interpolation" type.


That is to be expected. You're zero stuffing while interpolating, and then low pass filtering. But the filter doesn't know you're zero stuffing, and cannot make the optimizations that would save real-estate if it had known.

Mike