09-02-2020 06:49 AM
I instantiated the DSP48E2 having AREG = 1 and BREG = 1 (with CEA1 = 0, CEA2 = 1, CEB1 = 0 and CEB2 = 1) in order to have one pipeline stage for A and B input ports as in the following code. But in the simulation waveform P port returns the output at the same clock cycle where A and B inputs are given. (Here I made MREG = 0 and PREG = 0)
I believe that required control signals are set properly as in the code and can anyone tell me why this issue happens. Thanks in advance. (Simulation waveform is also attached here)
Here what I have created is simply P = A*B
DSP48E2#( .MASK(48'h000000000fff), // INITIAL VALUE : 48'h3fffffffffff .AREG(1), .BCASCREG(1), .BREG(1), .MREG(0), .PREG(0) ) DSP48E2_inst ( .ACOUT(ACOUT), .BCOUT(BCOUT), // .CARRYCASCOUT(CARRYCASCOUT), // .MULTSIGNOUT(MULTSIGNOUT), // .PCOUT(PCOUT), .OVERFLOW(OVERFLOW), .PATTERNBDETECT(PATTERNBDETECT), .PATTERNDETECT(PATTERNDETECT), .UNDERFLOW(UNDERFLOW), // .CARRYOUT(CARRYOUT), .P(P), // .XOROUT(XOROUT), .ACIN(30'd0), .BCIN(18'd0), .CARRYCASCIN(1'd0), .MULTSIGNIN(1'd0), .PCIN(48'd0), .ALUMODE(4'd0), .CARRYINSEL(3'd0), .CLK(CLK), .INMODE(5'd00000), .OPMODE(OPMODE), .RSTINMODE(0), .A(A), .B(B), .C(C), .CARRYIN(1'd0), .D(27'd0), .CEA1(1'd0), .CEA2(1'd1), .CEAD(1'd0), .CEALUMODE(1'd1), .CEB1(1'b0), .CEB2(1'b1), .CEC(1), .CECARRYIN(1'd1), .CECTRL(1'd1), .CED(1'd0), .CEINMODE(1), .CEM(1'd1), .CEP(1'd1), .RSTA(1'd0), .RSTALLCARRYIN(1'd0), .RSTALUMODE(0), .RSTB(1'b0), .RSTC(1'd0), .RSTCTRL(1'd0), .RSTD(1'd0), .RSTM(1'd0), .RSTP(1'd0) );
09-10-2020 02:32 AM
It looks like an issue with DSP48 similation model. What's the vivado version do you use? Can you try setting MREG to 1? Check if it makes a difference.
09-10-2020 12:47 PM - edited 09-10-2020 12:50 PM
I'm using vivado 2019.2 free version. When I select MREG = 1 while AREG and BREG to be zero, output will be visible at the same clock cycle. When MREG, AREG, BREG are kept at zero and PREG to be one, then output will be visible at the same clock cycle. But in reality output should be given with a one clock cycle latency when we have one pipeline inside the DSP, right ?
If we have 2 pipeline registers (let's say AREG = 1, BREG = 1 and MREG = 1) then output will be available with a one clock cycle latency, but it needs to have a 2 clock cycle latency because of the 2-deep pipeline registers.
09-11-2020 05:35 AM - edited 09-11-2020 05:37 AM
HI @kavinduvsomadas ,
In Vivado under language templates -> Device Primitive instantiation -> Ultrascale+ -> Arithmetic, there is a template of DSP48E2 slice.
Using that template and configure the same register settings (AREG=1,BREG=1,MREG=0,PREG=0) and simulating it shows the correct latency for Multiplication.
Can you check with this template and compare against your configuration.
09-12-2020 05:08 PM - edited 09-12-2020 05:10 PM
Hi @vkanchan Thank you for paying attention to my issue.
I checked it with the the instantiation template as you said, but unfortunately ended up with same results. Could it be some kind of issue in simulation from vivado simulator.
Can you please share your source code and testbench here and I'll check it and tell you whether it works fine or not.