cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
6,662 Views
Registered: ‎08-17-2015

JESD204B as TX

Jump to solution

Hi

 

I am using JESD204B IP as a TX on KC705board, and connect kc705 with TI's DAC37J82 EVM board

 

 

My test is based on simulation result (JESD204B open IP example).

 

From the result of simulation, the process of sending data through GTX is

 

1. Register setting (same as simulation configuration)

2. tx_aresetn goes "1"              --> this signal is comming from TI EVM board 

3. tx_sync goes "1"                   --> this signal is comming from TI EVM board

 

 

 

main handshake part is those signal

 

However, the big difference is 

1. rising point of "tx_aresetn"

2. tx_sync doesn't go high

 

I understand that there are some wrong configuration on IP & DAC board setting

My concern is how to approach to the point for debug

 

For example, 

Does "tx_sync doesn't go high " make JESD204B TX send wrong data to DAC?  so that DAC board can't send sync data to kc705 board?

 

or TI DAC board setting was wrong so that TI DAC board can't send tx_sync?

I just want to make sure JESD204B configuration setting is all correct.

It can be easy to debug for whole system.

 

 

----------------------------------------------------------------------------------------------------------------------------

I think this question should be on TI website.

But I believe that someone who is expert on this part see this question in Xilinx forum

 

when tx_sync goes high? (for subclass 1 operation)

it seems liek some random character (K/D/A/R/Q) goes to TI DAC37J82 EVM.

then, how it determine that it is sync or now with random character (K/D/A/R/Q).

Hope someone can answer this question too.

----------------------------------------------------------------------------------------------------------------------------

 

So, if the IP configuration setting and register setting is all same as IP example simulation,

Does it means that JESD204B setting on kc705 board doesn't have any problem?

so that I can just debug or change the configurations on TI DAC EVM board

 

 

I appreciate any comment or help

Thank you 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
12,494 Views
Registered: ‎08-01-2008
check the example design here on tested boards

http://www.xilinx.com/member/jesd204_eval/index.htm
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
12,495 Views
Registered: ‎08-01-2008
check the example design here on tested boards

http://www.xilinx.com/member/jesd204_eval/index.htm
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

Highlighted
Observer
Observer
700 Views
Registered: ‎06-09-2018

Has the page changed? I have JESD Lounge access and I don't see any reference designs - what happened?

0 Kudos