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Visitor gabel1989
Visitor
6,488 Views
Registered: ‎03-01-2012

LP filter and sample rate

Hei, 

 

Im trying to implemt an lp-filter as a IP modul in XPS. But him having som truble figure out what kind of samplerate my sysgen is running at.

 

I know that the from register is geting data at 24kHz, but what kind of sample rate is the 2n-tap filter running at? The clock pin in system generator is connect to my gclk(100MHz).

lp-filter.jpg
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8 Replies
Xilinx Employee
Xilinx Employee
6,481 Views
Registered: ‎08-02-2011

Re: LP filter and sample rate

It runs at whatever your sysgen clock rate is. In your case, 100MHz.

 

If you right click the MAC FIR block and select 'Look Under Mask' you will see the filter architecture.

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Explorer
Explorer
6,472 Views
Registered: ‎12-08-2010

Re: LP filter and sample rate

Hi.

 

First of all, it's bad idea to feed input signal through Register.

Registers are good for parameters setting, but not as signal input/output ports.

 

As Bwiec said, your system generator design (and FIR filter) will be running at sysgen_clk = 100 MHz.

But Register is connected to Microblaze with aid of AXI / PLB bus (with different clock).

So there is no guarantee that every new sample of input signal will be processed by filter only once.

 

 

In your case sysgen_clk = 100 MHz, fs_input (writing 'From Register') = 24 kHz. If we divide one by other, we'll get K = sysgen_clk / fs_input = 4166,67. It means that every input sample will be processed by filter 4166 times.

I assume that you are reading 'To Register' (output samples) with sampling rate = fs_input = 24 kHz. So if filter order is less than 4166, then nothing will be filtered at all.

 

Best Regards,
Vitaly.
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Visitor gabel1989
Visitor
6,465 Views
Registered: ‎03-01-2012

Re: LP filter and sample rate

Thanks for the great reply!

 

How wood you say the best way to feed singals to the FIR-filter, im using a AXI buss

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Explorer
Explorer
6,450 Views
Registered: ‎12-08-2010

Re: LP filter and sample rate

The best way to input signal in the System Generator model is 'Gateway In' block.

If you need to feed data directly from Microblaze (not from external port), then you should deal with synchronization between peripheral bus (AXI) and System Generator model. I.e, your System Generator model should process every input sample value only once. And your Microblaze core should write data to System Generator peripheral core only when this core is ready to process this data.

To do that you need to use some kind of additional FIFO buffer and Enable signals. 

 

Best Regards,
Vitaly.
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Xilinx Employee
Xilinx Employee
6,435 Views
Registered: ‎05-23-2008

Re: LP filter and sample rate

For interfacing to processor systems make use of the shared memories and as suggested make use of the FIFO shared memories as well. Also note that you have a export sysgen design as a Pcore option as well

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Visitor gabel1989
Visitor
6,427 Views
Registered: ‎03-01-2012

Re: LP filter and sample rate

So i shood use FIFO blocks insted of the from/to register block, is there an example somewhere that i can look at for some more info?

 

I tryed to use gateways, but how do i acsess them from microblaze?

 

 

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Xilinx Employee
Xilinx Employee
6,421 Views
Registered: ‎05-23-2008

Re: LP filter and sample rate

Hi you should be using shared memories. Also have a look in the sysgen UG as there are a couple of examples for using a shared memory

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Explorer
Explorer
6,420 Views
Registered: ‎12-08-2010

Re: LP filter and sample rate

Hi.

 

Yes, you can't directly access to gateway ports from Microblaze. Gateway ports are the best way to input/output external signals. Or you can write intermediate "glue" logic in HDL for interfacing gateway ports to Microblaze bus.

 

But it's easier to use FIFO blocks. The main problem here is to control data flow between Microblaze and signal processing core. It can be done with aid of Read/Write/Chip Enable signals and Empty/Full FIFO signals. Also you should use 'FIR Compiler' block as filter IP where you can turn on ND and RDY control signals (which let you control data flow).

 

Please read System Generator User Guide for more information (second chapter 'Hardware/Software Co-Design)':

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_user.pdf

 

You can find there a sample model 'AXI Embedded DSP Application with FIR Compiler and Shared Memory blocks' at page 210.

Best Regards,
Vitaly.
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