03-23-2014 05:55 PM
I'm trying to generate a high resolution, low frequency (10-200Hz) sine waveform using SysGen.
Spotting the DDS Compiler 6.0 block I've figured it might do the trick.
I also tried the xilinx/simulink help doc.
The problem is I can't seem to figure out how to set it right.
My model timimng is as follows:
FPGA clk period = 100n
Simulink system period = 100n
I've managed to control the output frequency for some extent (see the attached f.slx) by playing with the block's 'System Clock' and the 'Output Frequency' of channel 1.
Could somebody please direct me through the relevant block parameters for 50Hz for example?
A closed form formula would be more than appreciated.
BTW, I'd rather keep my FPGA clk period and Simulink clk period as is at the moment as they affect the operation of the rest of my simulation (and also my grasping of the simulink time dimension at the moment).
In addition, I would like to know if the block could be operated without a reset, i.e. generate output waveform from the first step. I've tried to unchek ARESETn but the DSS stoped outputting signals.
Attached please find a working model in which I managed to get a 50Hz low resolution sine waveform.
Also, as I mentioned I don't realy understand how did I get to 50Hz (trial and error).
Many thanks in advance.
03-23-2014 06:27 PM - edited 03-23-2014 06:31 PM
You can operate DDS without reset, it should not create any issue for frequery synthesis.
Here is the flow that used for 5.0, you may check if it helps
To generate 10 MHz using 100 MHz system clock at a frequency resolution of 0.4 Hz, phase width is 28 bits.
Phase Increment = (Fout/Fclk)*2^phase width.
= (10 * 10^6/100 * 10^6) * 2^28 = 26843545or 0x1999999
But when we input decimal 26843545 for data port we don't get expected output for sine/cosine.
The reason is Sysgen expects the value to be in fractional input for data port(PINC) which is (phase increment) /(2^phase width)
So the above formula for phase increment in Sysgen simplifies to
Fout/Fclk =(10 * 10^6/100 * 10^6) = 0.1 instead of 26843545.
This behavior seems to be different when compared to Coregen which need hex 1999999 for data port.
In addition, we may add a counter to the MDL design to vary PINC in steps of .001 to get modulating waveform
03-24-2014 12:10 AM
Thanks a lot for the quick reply but I'm still a bit confused.
Do I determine the 'system clock', 'phase increment' and 'phase width' which determine the output frequency or do I determine the 'system clock' and 'output frequency' which set the phase increment and width?
I'm integrating a DDS Compiler 6.0 block with only 'ARESETn' input at the moment.
In my model I'm using the following DDS parameters:
The output freq. I get on the scope is exactly 50Hz but I don't really understand why?
In addition, I can't seem to find the exact phase width parameter which might by because it is derived from the above parameters. In any case, I'm still lost.
03-24-2014 06:51 AM
there is another way to do this without the DDS:
you can use a CORDIC SINCOS block from the reference library and drive the input with a counter (A) which generates the phase from -pi to +pi with the number of samples your wish. You can then use an addtional counter (B) to driver the first counter (A) enable port at different speeds:
Use counter B and compare its output (>=) to your input setting (for example value from FROM Register block or external port) use the compare output to reset counter B and driver the enable of Counter A. Now you have a variable Frequency SIne and Cosine generator.
03-24-2014 11:05 AM
Thank you very much Markus,
I'll embrace your suggestion and let you know how did it go!
BTW, rereading (more than a couple) the docs again I figured out the relation between the various parameters and managed to generate a desired output frequency. However, as my output period is not an exact integer mutiplication of my PINC (phase increment) one can notice a crawling phase shift between the sine output and my counters after a while.
This, according to spec could also be solved using Rasterize mode but as far as I understand this mode is dedicated to much higher frequency. This is due to the Modulus (M) range limitation (9-2^14). The spec actually talks about a rational fraction, i.e. f_out=f_clk*N/M but I couldn't find which of the DDS parameters refers to N. If you do please let me know.
In addition, I would like to know if a single DDS could generate two different waveforms, rather than the single multiplication I generated when increasing the number of channels to 2.
Again, thanks a lot for the fruitful suggestions,
03-26-2014 12:35 AM
I've generated a sine waveform using the CORDIC 6.0 sysgen block as you suggested.
Now I won't to make my design more efficient.
My sine phase signal is generated using an limited up counter. As such, the phase signal has predefined values. This means a finite ROM LUT could be used to store the sine values on initialization same as in the rasterized mode of the DDS Compiler block.
Is there a way to set CORDIC in a rasterized mode?
Is it possible to make the DDS block generate a 50Hz sine waveform from a fpga_clk of 100ns using the rasterized mode?
03-02-2017 02:55 PM
Hello there my name is Tobi,
i am also trying to generate a waveform with DDS 6.0 but for a phased locked loop, i am trying to configure the DDS compiler but no luck, i want an output of 2*pi*1/500. any help would be much appreciated.