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Observer
Observer
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Registered: ‎04-29-2016

Make a pulse with non 50 percent duty cycle in sysgen

Hello to xilinx experts. It may be a basic problem but i can not build a pulse pattern with a duty cycle other than 50. I have tried combinations of all related sysgen blocks such as counter, delay, Addsub, etc. But I was not successful. Would you please guide me?
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