11-19-2018 11:48 PM
I‘m using FIR Compiler 7.2 within Labview 2018 to built a multichannel decimation FIR Filter for my A/D nodes on NI cRIO 9035 FPGA traget.
I‘ve got 80 channels sampled simutanously with 100kHz. The Data of these channels are interleaved packed as SGL in a 1-D-Array.
This Data Array should be filtered (digital lowpass) and decimated (1:5) by the Xilinx FIR.
I built an Application with only 1 Channel -> 1 Datapath in the FIR that worked. But I‘m not able (don’t know how) to scale it up to interleaved 80 Channel Data.
Is it possible to build a 80 Channel FIR for interleaved data or do I need 80 FIR Filters for my App?
11-27-2018 07:11 AM
You can make a multi channel decimating FIR filter. PG149, the FIR Compiler v7.2 product guide states in Chapter 4: "The number of channels supported by a filter core is specified in the filter Customize IP dialog box." You may or may not be able to make an 80 channel filter. I'm pretty certain you can make an 8 channel filter and instantiate it 10 times. PG149 is pretty good, it will tell you everything you need. It just takes a while to read and understand all of it. Experiment with different numbers of channels. Look at the trade offs between number of channels, resource usage and latency.