07-02-2013 10:43 AM
I've created a designed in Simulink which I then use the System Generator to compile into VHDL. However, upon compilation, I find that there are multiple clock signals which the VHDL blackbox uses as ports, called clk_1, clk_2048, and clk_4194304, all with respective enables. Looking into the VHDL code, it seems that each of these clocks are associated with different integrators, differentiators, etc in my design, with no rhyme or reason as to which signal is assocciated with which component. Can these all be tied to the primary clock? Or do they serve a particular purpose? The naming convention seems to suggest they do, but Sysgen offers no explanation as to their purpose. Thanks for your help!
07-02-2013 11:32 AM
I just realized - these are probably clocks for components operating at different data rates. Is this the case?
07-02-2013 12:25 PM
Sysgen shouldn't be creating different clocks for things running at different sample rates. It uses clock enables for that.
Are you using a multiple subsystem generator and defining multiple systems/clocks in the design?
07-02-2013 01:44 PM
As far as I know, no. I have one System Generator block at the highest level in my design, which specifies a single clock rate. I believe all of the components in the design are clocked off that signal. Looking over the VHDL more carefully, it does seem that the components where the clk_2048 and clk_4194304 signals are used are all subcomponents of the two 2048:1 CIC filters I've used.
07-02-2013 02:05 PM
07-02-2013 05:10 PM
07-03-2013 06:56 AM
07-06-2013 10:53 PM
Below is the entity definition from your _cw.vhd file, which only has one clock input. Did I miss something?
entity derp_cw is
acq_en: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 25.0 ns (40.0 Mhz)
man_freq: in std_logic_vector(15 downto 0);
pm_en: in std_logic;
rf_in: in std_logic_vector(15 downto 0);
rst: in std_logic;
i_out: out std_logic_vector(15 downto 0);
nco_addr: out std_logic_vector(13 downto 0);
pinc_out: out std_logic_vector(59 downto 0);
q_out: out std_logic_vector(33 downto 0)