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Visitor chilton
Visitor
4,957 Views
Registered: ‎07-02-2013

Multiple Clock Signals

I've created a designed in Simulink which I then use the System Generator to compile into VHDL. However, upon compilation, I find that there are multiple clock signals which the VHDL blackbox uses as ports, called clk_1, clk_2048, and clk_4194304, all with respective enables. Looking into the VHDL code, it seems that each of these clocks are associated with different integrators, differentiators, etc in my design, with no rhyme or reason as to which signal is assocciated with which component. Can these all be tied to the primary clock? Or do they serve a particular purpose? The naming convention seems to suggest they do, but Sysgen offers no explanation as to their purpose. Thanks for your help!

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9 Replies
Visitor chilton
Visitor
4,955 Views
Registered: ‎07-02-2013

Re: Multiple Clock Signals

I just realized - these are probably clocks for components operating at different data rates. Is this the case?

 

Thanks,

Andy

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Xilinx Employee
Xilinx Employee
4,946 Views
Registered: ‎08-02-2011

Re: Multiple Clock Signals

Sysgen shouldn't be creating different clocks for things running at different sample rates. It uses clock enables for that.

 

Are you using a multiple subsystem generator and defining multiple systems/clocks in the design?

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Visitor chilton
Visitor
4,940 Views
Registered: ‎07-02-2013

Re: Multiple Clock Signals

As far as I know, no. I have one System Generator block at the highest level in my design, which specifies a single clock rate. I believe all of the components in the design are clocked off that signal. Looking over the VHDL more carefully, it does seem that the components where the clk_2048 and clk_4194304 signals are used are all subcomponents of the two 2048:1 CIC filters I've used. 

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Visitor chilton
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4,940 Views
Registered: ‎07-02-2013

Re: Multiple Clock Signals

And thanks for your reply :D

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Xilinx Employee
Xilinx Employee
4,936 Views
Registered: ‎08-02-2011

Re: Multiple Clock Signals

Hmm what version of the tools? Can you post your model and/or the _cw.vhd generated by sysgen?
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Xilinx Employee
Xilinx Employee
4,931 Views
Registered: ‎08-02-2011

Re: Multiple Clock Signals

It looks like sysgen will create clock ports for you if you selected the 'Expose Clock Ports' option in the sysgen token for the 'multirate implementation'
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Visitor chilton
Visitor
4,920 Views
Registered: ‎07-02-2013

Re: Multiple Clock Signals

Thanks again for the responses. I've attached my  _cw.vhd file; I recompiled it with "Clock Enables" as the Multirate Implementation choice, and the problem persists. 

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Visitor chilton
Visitor
4,896 Views
Registered: ‎07-02-2013

Re: Multiple Clock Signals

Still there?

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Xilinx Employee
Xilinx Employee
4,869 Views
Registered: ‎11-28-2007

Re: Multiple Clock Signals

Below is the entity definition from your _cw.vhd file, which only has one clock input. Did I miss something?

 

entity derp_cw is
  port (
    acq_en: in std_logic;
    ce: in std_logic := '1';
    clk: in std_logic; -- clock period = 25.0 ns (40.0 Mhz)
    man_freq: in std_logic_vector(15 downto 0);
    pm_en: in std_logic;
    rf_in: in std_logic_vector(15 downto 0);
    rst: in std_logic;
    i_out: out std_logic_vector(15 downto 0);
    nco_addr: out std_logic_vector(13 downto 0);
    pinc_out: out std_logic_vector(59 downto 0);
    q_out: out std_logic_vector(33 downto 0)
  );
end derp_cw;

Cheers,
Jim
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