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Participant
Participant
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Registered: ‎10-07-2016

Need to Flush Data path & FIR filters

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Hi,

I'd like to verify that the data path needs flushed and if there are any embedded IP techniques to flush it.

My Data path is using the Xilinx IP FIR filters, FIFOs and switches, all of which are AXIS (streaming AXI). The signal being processed has 3 sections,  leading ramp up samples, the desired samples and then trailing ramp down signals. I'm doing the design through IP integrator.

I'm assuming the signal has to be flushed through the datapath once the last ramp down sample is clocked into it with the AXIS handshaking. I think it along with the other ramp down samples are stuck in the data path and there is no automatic flushing or pushing of this sample to the output. Is this true?

Does the IP have built in features to do this?

I am thinking about using the TLAST signal on the last ramp down sample as an indicator that the last sample is on the output. Once the last sample is clocked into the input, this would be followed with dummy samples until the TLAST was seen on the output.

When a new signal needs to be processed, these dummy samples are in the data path. They would also need to be flushed from the data path with the new signal. The dummy samples would have to be ignored (or not shown on the output). I also thought about using the AXIS reset signal to get back to a known unfilled pipeline state once the last ramp down sample is output.

Is there a better way to do this?

Thanks,

Chuck

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Xilinx Employee
Xilinx Employee
716 Views
Registered: ‎09-18-2018

Hi @chuck_s ,

Use of TLAST would be the better way to flush out the data. I checked it and the internal core needs to be supplied with valid zeros samples for the filter output to emerge. The TLAST and dummy valid zeros is the way to this. The TLAST will also be provided at output and this can be used to qualify output data samples.

 

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Xilinx Employee
Xilinx Employee
738 Views
Registered: ‎09-18-2018

Hi @chuck_s ,

The FIR compiler has reset mechanism with data vector reset, which clears out all the data present in the FIR compiler core.

Please go through the Reset section in the FIR PG 149 on page 12 and see if it can suit your design.

 

 

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Participant
Participant
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Registered: ‎10-07-2016

Vkanchan,

Thanks, I think I'll do that to help make sure the 1st samples go out when I need them to. I don't like using resets in the middle of operations but that may be the best technique. 

What about pushing the last sample through the filter? This is the flushing. What do you recommend? Using the TLAST feature on the last sample and clocking (AXIS handshaking) 0's through until TLAST comes out?

Thanks,

Chuck_s

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Xilinx Employee
Xilinx Employee
717 Views
Registered: ‎09-18-2018

Hi @chuck_s ,

Use of TLAST would be the better way to flush out the data. I checked it and the internal core needs to be supplied with valid zeros samples for the filter output to emerge. The TLAST and dummy valid zeros is the way to this. The TLAST will also be provided at output and this can be used to qualify output data samples.

 

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Participant
Participant
706 Views
Registered: ‎10-07-2016

Vkanchan,

Thanks for checking the flushing operation. I do appreciate it. 

It would be nice if there were a feature in the AXIS IP to do flushing.

Thanks for your help,

Chuck

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