11-13-2018 10:25 AM
Our project uses LogicCore FFT IP module and we are upgrading from version 7.1 on Virtex6 platform to version 9.1 on Zynq platform.
I am trying to make sense of version 7.1 to 9.1 port mapping - cycle accurate - since the module is interfaced to memories on both read and write side and does that in bursts - so signals getting asserted or de-asserted one cycle too early or late leads to errors (that I am seeing - erroneous values).
It will be very kind if someone can help with two things -
1. What to connect the following new signals to -
Also, How should I connect my logic that used to check for the following signals in previous version -
2. I also saw when I instantiate IP 9.1 a VHDL testbench is generated. The same is NOT done for IP version 7.1. I wish to use as close/similar a TB as possible for both IPs to draw comparison - but again I am stuck with the Q1 above.
It will be very kind if someone can tell me if there is any auto generated TB with 7.1 like 9.1 and where it is - or if there is a process to do it.
Thanks and sincerely
11-13-2018 08:17 PM - edited 11-13-2018 08:18 PM
Please look at https://forums.xilinx.com/t5/DSP-IP-and-Tools/Question-about-FFT-9-1-IP/td-p/908648, and let us know if there are further questions.
01-10-2019 12:27 AM
Please look at https://forums.xilinx.com/t5/DSP-IP-and-Tools/Question-about-FFT-9-1-IP/td-p/908648 buyessay, and let us know if there are further questions.
Thanks for sharing this link. It makes everything clearer to me at this point.