04-21-2018 07:08 AM
Hello, I want to build a QPSK-modulator with interpolation filter. The simulink simulation could run without any error though the result is not right (all points in constellation occurs in zeros). I have checked all the inputs of this model, and they works fine. By the way, since output data rate is faster than input data rate, I have followed the instruction of page 196 in UG897, setting output rate to 1.0, i.e.
In multiple clock hardware designs, the clock period of the port interface should be computed using the connected “clocked subsystem domain”. By default, “synchronous system clock” source is used by all the ports but for asynchronous clock hardware designs it is necessary to explicitly specify the clock sources of every port (e.g., if the output port clock is different than the block's input port clock). Note: You must set the sample rate to ‘1.0’ to all output ports of multiple independent clock black box designs; it automatically set the output ports to the destination clock subsystem period. SysgenPortDescriptor provides a method ‘setRate’, which allows you to explicitly set the rate of a port. Example: port('<port_name>').setRate(1.0)
I want to find more details about this problem. So I run SG simulation by press generate button in SG token. It remind there is an error in one input gateway.
Errors occurred during netlist generation. Error reported by S-function 'sysgen' in 'gm_commqpsktxhdl/Subsystem1/Gateway In3': A summary of Sysgen errors has been written to 'C:/Users/Luckfyzhang/Desktop/Wkdesktop/project/hdltx_hdl/gm_commqpsktxhdl_sysgen_error.log
This is not clear for me to know how to fix it and there is no more details in that log file actually. Can anyone help me?
04-22-2018 11:29 PM - edited 05-13-2018 11:27 PM
Here, I enclosed my project gm_commqpsktxhdl.slx. Before you run this project you need to load qpskwkspace.mat file. I appreciate any suggestions.
04-24-2018 08:54 AM
05-10-2018 07:34 AM
Thanks for your reply. Actually, when I changed system generator language from VHDL to Verilog, this problem was solved immediately. I guess this would be a software bug.
Besides, in my Simulink project, I still have several problems.
Can you provide me some help?
Thanks for reading.
05-10-2018 10:50 AM
I set Simulink System Period to Ts, with output rate to 1 (using setRate method) as I said in my
formal post in this thread and I set all input sample time to 4*Ts. I think this would be right as
there is a interpolation filter with up-sampling parameter of 4 inside my blackbox model. I set all
other sample time to -1. But the constellation was in complete chaos. However, when I set sample
period of output data to 4*Ts, the constellation was right. Why? After up-sampling, should not
output rate be increased?
It's a little difficult to say for sure. Can you set the block icon display to show normalized sample periods and post a screenshot showing your black box? Also, can you post your _config.m file.
I know that when you set clk and clk_enable as pairs, System Generator would hide these ports. So
what is real speed of clk? I mean when I want to get output rate of 1/Ts, frequency of input clk
should be 1/Ts of 1/(4*Ts)?
In a single clock domain sysgen design, there obviously just one clock and the other sample rate domains are driven by clock enables generated at some rational factor by that one clock. The idea is that you use the 'Hardware Clock Period' which defines the constraint that's put on the clock (i.e. the 'real' clock rate). Call that 10ns for 100MHz clock. Then you set the 'Simulink System Period' which is a normalization factor. Call it 1. In your case, you have two 'sample rate domains' (my term) with periods 1 and 4 (granularity relative to simulink system period).
So now when you integrate this into a real system and hook up a 100MHz clock, the input to your interpolator (set to a period of 4) is running at 25MSPS (i.e. it will accept a new sample every 4 clocks) and the output will be running at 100MSPS (new sample every clock).
05-13-2018 11:26 PM