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Explorer
Explorer
496 Views
Registered: ‎10-16-2018

Noisy output from FIR compiler 7.2

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Hi ,

I am trying to impelement FIR compilers in my seystem design. 

I depended on TFilter in my design for the FIR filter. The filter paramters (frequency response) are shown in the first attached picture.

The interface connections between the DDS compiler (16 kHz oscillator) and the FIR complier are shown the second attached picture. 

After I imported the coeffecents file in FIR IP core, then I run the a simulation to check the output of the FIR filter. The third attached picture shows a noisy output for this filter !

The FIR filter type is "Single Rate", the fourth attached picture shows the frequency response for the imported coeffecints inside the FIR compiler.

Pls, how to fix the output signal to become smooth like the input?

Thanks. 

Tags (1)
Filter_parameters_T2.JPG
Design.JPG
Simulation.JPG
freq_response_FIR_IP.JPG
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1 Solution

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485 Views
Registered: ‎06-21-2017

Re: Noisy output from FIR compiler 7.2

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What is your input sample frequency?  The frequency listed in your configuration is 0.001MHz.  You are probably sending samples to the filter faster than it can process the data.  Change the Input Sampling Frequency in the Channel Specificatin tab to the system clock frequency.  In general, you should always monitor the s_axis_tready in a simulation even if you don't plan to use it in system just to be sure you are not trying to send data to the filter when it is not ready.

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5 Replies
486 Views
Registered: ‎06-21-2017

Re: Noisy output from FIR compiler 7.2

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What is your input sample frequency?  The frequency listed in your configuration is 0.001MHz.  You are probably sending samples to the filter faster than it can process the data.  Change the Input Sampling Frequency in the Channel Specificatin tab to the system clock frequency.  In general, you should always monitor the s_axis_tready in a simulation even if you don't plan to use it in system just to be sure you are not trying to send data to the filter when it is not ready.

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Explorer
Explorer
468 Views
Registered: ‎10-16-2018

Re: Noisy output from FIR compiler 7.2

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Hi @bruce_karaffa ,

Thank you for your precise notes.

I changed the input sampling frequency to be equal the system clock signal (300 MHz). The noise is redunced as shown in the attached picture. 

I will moniter TREADY signal and reach you again .

Thanks .

16kHz_betterT2_300MHz_inFS300MHz.JPG
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Explorer
Explorer
462 Views
Registered: ‎10-16-2018

Re: Noisy output from FIR compiler 7.2

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Hi @bruce_karaffa ,

After I monitered TREADY signal , I found it is always 1 as it is required.

Kindly, see the attached two picture.

The first one is just a zoom veiw for the simulated signals.

What I can do to enhance the signal further?

Thanks,

zoom.JPG
16kHz_betterT2_300MHz_inFS300MHz_Ready.JPG
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418 Views
Registered: ‎06-21-2017

Re: Noisy output from FIR compiler 7.2

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@ahmed_alfadhel  I'm not sure what is happening.  Your input sine wave doesn't look very smooth.  How many bits are you using in your phase accumulator for the DDS?

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Explorer
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Registered: ‎10-16-2018

Re: Noisy output from FIR compiler 7.2

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Hi @bruce_karaffa ,

I used 12 bits for the DDS output, devided into 6 bits for "Output Width" and 6 bits for "Phase Angle Width". As indicated in the attached picture.

Looking forward your reply.

Thanks, 

DDS_data_width.JPG
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