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Registered: ‎02-01-2020

Non Memory Mapped Ports for Basys 3 using Vivado System Generator and Hardware Co-simulation

Hi there, Xilinx comunity!

I'm glad to use somehow Xilinx's Vivado based System Generator 2016.2 for Matlab - Simulink R2015b, and hardware co-simulation on a Basys 3 FPGA - Artix 7. It's a nice powerfull tool that allows us to test most of the control laws and loops designed in Simulink on faster computation platform like an FPGA.

The big question is: How can I use the Gateway blocks from the Simulink model, in such way that the input gateway will act as a real hardware digital input pin on the board or the output to act as a real harware digital output pin during the co-simulation? Or how can I have hardware feedback from my FPGA via jTAG during co - simulation?

P.S.: I know that there are IoB constrain options in the 'Implementation' tab of the gateway block. I have entered there physical pin and pad coordinates, i have done that, it work on hardware (the LED is linked to the switch according to the model), but during co-simulation, no Simulink sub-system inputs or outputs attached to the jTAG co-simulation block are created. Is this an issue or you need to do something more special to obtain that feedback ports? This means that I cannot receive (in Simulink) the signal (from a swith on the board for example), or send a signal out from the Simulink model (to a LED on the board for example). Some time ago, this feature was available within ISE Design Suite based System Generator on Spartan 6 based and other FPGA boards. This feature was available as Non Memory Mapped Ports which were possible to be configured from the advanced co-simulation setting menu in the System's Generator Token. In the Vivado based System Generator, there are only a few options that are not related to hardware I / O pins of the FPGA Board. The user manual of the System Generator doesn't provide any information about this kind of feature anymore. But, I'm sure that it is possible to acheive it again! 

So, is there any solution to this issue in the actual versions of System Generator? All I want is to use the board as a real - time rapid control prototyping or hardware in the loop platform within Simulink. I think it is possible, at least that the co-simulation is performed via jTAG connection to the host computer. jTAG is way faster than usual UART serial communication, and is very often used with DSP platforms as a debugging probe.

Best regards,

Pintilie Lucian - Nicolae...

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Registered: ‎02-01-2020

Re: Non Memory Mapped Ports for Basys 3 using Vivado System Generator and Hardware Co-simulation

After almost a month first results came on after researching over this issue:

First: To avoid all software incompatibility issues, use Matlab - Simulink R2015a and Vivado System Edition 2016.2;

Second: To support Basys 3 in the System Generator co-simulation target list follow this guide (SysGen 2016.2 User Manual page 15 - "Specifying Board Support in System Generator"), and remember to add the Digilent boards support package in C:\Xilinx\Vivado\2016.2\data\boards\ (as described here - Vivado Version 2015.1 and Later Board File Installation (Legacy) ), and according to SysGen 2016.2 U.G. you need to create a "startup.m file" and point to "C:\Xilinx\Vivado\2016.2\data\boards\";

Third: To support non-memory mapped ports, we need build a model that contains a simple, plain, "as-is" "gateway input" and "gateway output" wired together so that the "flow of information" can be done via the uploaded model as shown in attached figure "Initial_model.png". From the connecting bus attach another "gateway output", but this time, in the "Implementation" tab, we will specify some hardware constraints (these coordinates can be obtained from the  "part0_pins.xml" file located in "C:\Xilinx\Vivado\2016.2\data\boards\board_files\basys3\C.0"), as shown in attached figure "Constraint_output.png";

Fourth: Set SysGen token settings to support "Basys3 C.0" as default board and use "Hardware Co-simulation (Jtag)" as default compilation method. (The board model must be showing there if all the steps until now were fullfiled);

P.S.: If SysGen says that compilation is done, and no hardware co-simulation jTAG library block is created, it might be this problem - see attached figure "UnCheck.png". Uncheck "Burst mode" found if we click the "Settings" button after the chosen "Compilation" method in SysGen;

Fifth: A "jTAG co-simulation" library with the plain "Gateways I / O" shall be created (see attached figure "jTAG_Block.png");

Sixth: Use the jTAG co-simulation to build the "real - time debugging model" as shown in attached figure "Full_model.png");

Seventh: Enjoy a real - time Simulink based toggle switch with real hardware output (see attached figure "20200317_004020.jpg")!

Raised questions after this journey:

- Can this model be extrapolated to a more complex cheap FPGA - based Simulink Hardware In the Loop system???

- Can we SEND and RECEIVE digital signal information from hardware I/O during co-simulation???

- Why AXI-4 LITE based gateways cannot be used (for GPIO) during hardware co-simulation??? 

- Is there any way to bring back old good Board Description Builder feature in the new Vivado based System Generator???

Thank you for attention!

Constraint_output.png
Initial_model.png
UnCheck.png
jTAG_Block.png
Full_model.png
20200317_004020.jpg
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Registered: ‎02-01-2020

Re: Non Memory Mapped Ports for Basys 3 using Vivado System Generator and Hardware Co-simulation

Two other raised questions regarding Non Memory Mapped Ports in Vivado based System generator are answered here:

- Can this model be extrapolated to a more complex cheap FPGA - based Simulink Hardware In the Loop system???

Yes we can! Using the jTAG data Exchange channel between host PC and Target Board! (see the attached figures);

- Can we SEND and RECEIVE digital signal information from hardware I/O during co-simulation???

According to the attached picture of the Simulink model and the hardware interraction proof, there seems to be a possibility to some-how initiate a communication channel via jTAG by interconnecting two gateway blocks in the model (IN and OUT). These two blocks are the INPUT and OUTPUT ports of the resultant jTAG communication block. The Gateways that are hardware contraint, doesn't provide any feedback ports back into PC co-simulation! So we need to create them virtually by inter-connecting two hardware UN-CONSTRAINT gateways! In my model I have used an OR gate to "route the information" between target hardware board and the PC host. I think this is somehow a proofing experiment that shows the FPGA capability of doing Parallel Computations (please correct me if I am wrong!). So, if these things are possible, I think the problem is partially solved!

P.S.: Notice the fact that I have changed the 'V17' switch state and the 'U16' LED has lighted up, and also, a feedback in the simulation has appeared (both on display and scope). All according to the model! If I stop the simulation the LED keeps the last state and, the interraction between button and LED stops!

Next questions:

- How do we access the xADC, UART, SPI, I2C, PWM???

- Do we need to hardware emulate these functions inside the FPGA or they are natively accesible via AXI within co-simulation???

I hope these informations shall be usefull for someone! 

Thanks for your attention!

Full_feedback.png
20200317_121438.jpg
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