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Registered: ‎02-01-2020

Non Memory Mapped Ports for Basys 3 using Vivado System Generator and Hardware Co-simulation

Hi there, Xilinx comunity!

I'm glad to use somehow Xilinx's Vivado based System Generator 2016.2 for Matlab - Simulink R2015b, and hardware co-simulation on a Basys 3 FPGA - Artix 7. It's a nice powerfull tool that allows us to test most of the control laws and loops designed in Simulink on faster computation platform like an FPGA.

The big question is: How can I use the Gateway blocks from the Simulink model, in such way that the input gateway will act as a real hardware digital input pin on the board or the output to act as a real harware digital output pin during the co-simulation? Or how can I have hardware feedback from my FPGA via jTAG during co - simulation?

P.S.: I know that there are IoB constrain options in the 'Implementation' tab of the gateway block. I have entered there physical pin and pad coordinates, i have done that, it work on hardware (the LED is linked to the switch according to the model), but during co-simulation, no Simulink sub-system inputs or outputs attached to the jTAG co-simulation block are created. Is this an issue or you need to do something more special to obtain that feedback ports? This means that I cannot receive (in Simulink) the signal (from a swith on the board for example), or send a signal out from the Simulink model (to a LED on the board for example). Some time ago, this feature was available within ISE Design Suite based System Generator on Spartan 6 based and other FPGA boards. This feature was available as Non Memory Mapped Ports which were possible to be configured from the advanced co-simulation setting menu in the System's Generator Token. In the Vivado based System Generator, there are only a few options that are not related to hardware I / O pins of the FPGA Board. The user manual of the System Generator doesn't provide any information about this kind of feature anymore. But, I'm sure that it is possible to acheive it again! 

So, is there any solution to this issue in the actual versions of System Generator? All I want is to use the board as a real - time rapid control prototyping or hardware in the loop platform within Simulink. I think it is possible, at least that the co-simulation is performed via jTAG connection to the host computer. jTAG is way faster than usual UART serial communication, and is very often used with DSP platforms as a debugging probe.

Best regards,

Pintilie Lucian - Nicolae...

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Registered: ‎02-01-2020

After almost a month first results came on after researching over this issue:

First: To avoid all software incompatibility issues, use Matlab - Simulink R2015a and Vivado System Edition 2016.2;

Second: To support Basys 3 in the System Generator co-simulation target list follow this guide (SysGen 2016.2 User Manual page 15 - "Specifying Board Support in System Generator"), and remember to add the Digilent boards support package in C:\Xilinx\Vivado\2016.2\data\boards\ (as described here - Vivado Version 2015.1 and Later Board File Installation (Legacy) ), and according to SysGen 2016.2 U.G. you need to create a "startup.m file" and point to "C:\Xilinx\Vivado\2016.2\data\boards\";

Third: To support non-memory mapped ports, we need build a model that contains a simple, plain, "as-is" "gateway input" and "gateway output" wired together so that the "flow of information" can be done via the uploaded model as shown in attached figure "Initial_model.png". From the connecting bus attach another "gateway output", but this time, in the "Implementation" tab, we will specify some hardware constraints (these coordinates can be obtained from the  "part0_pins.xml" file located in "C:\Xilinx\Vivado\2016.2\data\boards\board_files\basys3\C.0"), as shown in attached figure "Constraint_output.png";

Fourth: Set SysGen token settings to support "Basys3 C.0" as default board and use "Hardware Co-simulation (Jtag)" as default compilation method. (The board model must be showing there if all the steps until now were fullfiled);

P.S.: If SysGen says that compilation is done, and no hardware co-simulation jTAG library block is created, it might be this problem - see attached figure "UnCheck.png". Uncheck "Burst mode" found if we click the "Settings" button after the chosen "Compilation" method in SysGen;

Fifth: A "jTAG co-simulation" library with the plain "Gateways I / O" shall be created (see attached figure "jTAG_Block.png");

Sixth: Use the jTAG co-simulation to build the "real - time debugging model" as shown in attached figure "Full_model.png");

Seventh: Enjoy a real - time Simulink based toggle switch with real hardware output (see attached figure "20200317_004020.jpg")!

Raised questions after this journey:

- Can this model be extrapolated to a more complex cheap FPGA - based Simulink Hardware In the Loop system???

- Can we SEND and RECEIVE digital signal information from hardware I/O during co-simulation???

- Why AXI-4 LITE based gateways cannot be used (for GPIO) during hardware co-simulation??? 

- Is there any way to bring back old good Board Description Builder feature in the new Vivado based System Generator???

Thank you for attention!

Constraint_output.png
Initial_model.png
UnCheck.png
jTAG_Block.png
Full_model.png
20200317_004020.jpg
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Registered: ‎02-01-2020

Two other raised questions regarding Non Memory Mapped Ports in Vivado based System generator are answered here:

- Can this model be extrapolated to a more complex cheap FPGA - based Simulink Hardware In the Loop system???

Yes we can! Using the jTAG data Exchange channel between host PC and Target Board! (see the attached figures);

- Can we SEND and RECEIVE digital signal information from hardware I/O during co-simulation???

According to the attached picture of the Simulink model and the hardware interraction proof, there seems to be a possibility to some-how initiate a communication channel via jTAG by interconnecting two gateway blocks in the model (IN and OUT). These two blocks are the INPUT and OUTPUT ports of the resultant jTAG communication block. The Gateways that are hardware contraint, doesn't provide any feedback ports back into PC co-simulation! So we need to create them virtually by inter-connecting two hardware UN-CONSTRAINT gateways! In my model I have used an OR gate to "route the information" between target hardware board and the PC host. I think this is somehow a proofing experiment that shows the FPGA capability of doing Parallel Computations (please correct me if I am wrong!). So, if these things are possible, I think the problem is partially solved!

P.S.: Notice the fact that I have changed the 'V17' switch state and the 'U16' LED has lighted up, and also, a feedback in the simulation has appeared (both on display and scope). All according to the model! If I stop the simulation the LED keeps the last state and, the interraction between button and LED stops!

Next questions:

- How do we access the xADC, UART, SPI, I2C, PWM???

- Do we need to hardware emulate these functions inside the FPGA or they are natively accesible via AXI within co-simulation???

I hope these informations shall be usefull for someone! 

Thanks for your attention!

Full_feedback.png
20200317_121438.jpg
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Registered: ‎08-10-2018

Please help basys3 vivado system generator 2017.2 matlab 2016a not detecting basys3 even after including board files, plz include startup.m file and steps clearly

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Hey! Hi there! Thank you for feedback! I hope this will help you! In my second answer posted in this thread I wrote something like this: "....First: To avoid all software incompatibility issues, use Matlab - Simulink R2015a and Vivado System Edition 2016.2...." Why i have came to this conclusion... After a long period of unsleeped nights, tons of failed Vivado installations, hundreds of versions of Matlab installations and Vivado docentation research I have seen that Basys 3 is a 2016 board release of the Artix 7 FPGA core... So, the software that worked for me, was exactly the version that match with the release date. Now, how i have added the board to hardware co-simulation? Firstly first, i want to tell you, that this kind of board, supports hardwaee co-simulation function ONLY on Matlab R2015a, and Vivado System Edition 2016.2. I have tried different versions but the boards shows grayed out in the list, or, on recent versions, it doesn't show at all.... In the second post, I have als posted some links. The best "source of inspiration" was the User Guide of Vivado System Generator 2016.2, wich tells us how to add third party hardware co-simulation boards to System Generator (see table of contents). The procedure is described also in the second link! MathWorks also has some good documentation on how to edit that startup file, and even tells you, what commands to use and how to edit it! Basicly, you need to specify in that startup file, where is your Vivado "Boards" directory located on the "C:\>" drive... Remind that you have added some board support package files to Vivado, in order to support Digilent related boards! That directory must be declared in the startup file! I also think, that in the System Generator used guide, there is an example of startup file content... So, please read carefully!

 

I hope this recommandations will help you, solve this issues!

God bless you and your family!

Best regards, Pintilie Lucian - Nicolae!

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Registered: ‎02-01-2020

Hi there!

Let's clarify these things even further:

1. Make sure that you have Vivado System Edition 2016.2 and Matlab - Simulink R2015a;

2. Make sure that you have started Matlab - Simulink from System Generator shortcut "as Administrator";

3. In the Matlab's command window type "which startup.m": (If there's no "startup.m" file create one in "C:\Xilinx\Vivado\2016.2\scripts\sysgen\matlab\startup.m" from the menu "New --> Script");

xil1.jpg

4. Add the following contents to the "startup.m" file:

addpath([[getenv('XILINX_VIVADO')] '/scripts/sysgen/matlab']);
xilinx.environment.setBoardFileRepos({'C:/Xilinx/Vivado/2016.2/data/boards/board_files'});

(The directory "C:/Xilinx/Vivado/2016.2/data/boards/board_files" contains the Digilent - Basys 3 board support package files);

xil2.jpg

5. Save the "startup.m" file from Matlab editor;

6. Restart Matlab (don't forget to start Matlab from System Generator Shortcut);

7. The board will now show in the co-simulation list of the System Generator token in Simulink.

 

I hope this was helpful!

Thank you again for feedback!

Have a nice day!

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Registered: ‎08-10-2018

Thank you sir for such a nice tutorial clarifying doubts with faster response before i tried same way from one help pdf also but some times my board not detecting, i will also with ur solution and i will follow sir actually i am trying upcounter with  basys3  in simulink system generator controlling updown mode from hardware cosimulation plz help in delays it is taking so much time to generate bit file some time blinking but i can't see the speed of led

in sys gen token clocking tab

100Mhz --> 10nses??  10e-9??  w5 as clock pin plz suggest the how to give delay for 1 sec, 2sec, 5sec for diff up counters.. and why its taking 1 hour for generating bitstream in hwsw cosimulation waiting for your reply

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Registered: ‎02-01-2020

Hi there!

As I read your post, I consider helpful for you the following aspects>

1. Clarifying what means hardware co-simulation and bitstream - Vivado generation. Hardware co-simulation allows you to test the model directly from Simulink. This technique is best known in the academic comunity as Rapid Control Prototyping. It may help you to generate, load, run and test the bitstream directly from Simulink, and it even helps you to change model parameters during the simulation (let's say that you set the total simulation time to "inf" [infinity] and the simulation runs forever until you hit the stop button). Doing like so it will help you to fine-tune your model or bitstream program. (this function works only on R2015a). Bitstream generation, (as it says) only generates the executable ".bit" file that can be uploaded to the board using Vivado. By using the bitsream method you cannot fine - tune the model from Simulink.

2. Why the process takes 1 hour? Actually not the compilation process or bit-stream generation process takes this time. It is the "synthesis" step that takes so much time. In the FPGA's world. Synthesis means "translating" the VHDL / Verilor / Simulink code - program in logic gates, multiplexers, and other digital components. I think (but I am not so sure) that this process can be speeded up by increasing the performance of yor PC.

3. Timing and delay, can be adjusted by using "Delay" blocks in your model (the special "Delay" blocks that come with the System Generator's toolbox not the Simulink ones). Also, you need to set the correct "Sample Time" all over the model. Sample time parametter, cand be set from three points in a System Generator based model. First from the "Model Configuration Parametters" menu (I recommend: "Solver: Discrete - no continuous state", and "Fundamental sample time: 1e-4" (10^-4)). Second place that sample time cand be set, is the "Clocking" tab from the System Generator's token (I recommend you to specify the "Simulink system period" as 1 second, and the clock pin as the Artix-7 Basys 3 datasheet says 'W5', and also the period that matches 100 [MHz] - some ns). Third place that you can specify the sample time is in the block properties of any Xilinx block (ex. the gateway IN block - I also recommend the sample time 1 second).

4. The end time of the simulation (or the total time of simulation) can be set according to the time necesary for the process to complete (ex. if an ehight - bit counter is used to count to maximum, the total time of simulation shall be 255. Why? Because [2 ^ 8] - 1 = 255 - and counting from zero, it means that we have 256 steps).

I hope this information was usefull.

Have a nice day!

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Registered: ‎08-10-2018

Sir i am implementing counter in system generator hw-cosim doesn't consists of ports, even i am using or logic and mux logic also please suggest if design consists of more input & output in your design single gpio if my design has 4 inputs and 8 outputs how to generate hw-cosim block with ports waiting for your reply i tried many ways i didn't get output sir

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Registered: ‎04-28-2020

Hi Pintilie Luci

I have followed your steps and most to the issues were solved, thank you.

I have one last one: when click-in the run button in Simulink, I get an error: Error 0001: Could not find JTAG device xc7a35ti. Block: 'fpga_test4/fpga_test4 hwcosim'  I performed a test in HDL verified and there is report "test connection successfully".

Ajutor Te rog

Andrei

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Hi there!

According to this answer: https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/JTAG-Hardware-cosimulation-help-for-XC7A35T-arty-board/td-p/835921

...the issue may be related to the jTag driver used by System Generator... Modifying some parts of the board.xml file or part0_pin.xml, may help...

My experience say, that these errors are generated by non-administrative execution of the System Generator  app shortcut... Choose "Run as Administrator".

It may also be possible that the board you are using to be incompatible with Vivado 2016 or Matlab - Simulink 2015a. Basys 3 seems to be released in the same year with the software... You must see if the specified board matches the version...

 

Sorry, this is all that I can provide...

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Registered: ‎04-28-2020

That answer makes no sense to me.

the Arty A7-35 shows up in the "system generator" - boards option. if I apply that "solution" the board will no longer be present in the list. I have some issues with "incomplete" answers

 

Now regarding your advice, I have another small question. I noticed that sometimes the "JTAG cosim" block is generated with ports, some times, and sometimes without ports.... I don't realize what I am doing differently???

Multumesc

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The ports are not showing on the Hardware co-simulation block, if you set hardware IoB constrains. A solution to this isssue, is to add in parallel another gateway, that has no hardware constraints. And after compilation, you will have acces to the "bus" via the unconstrained gateways. See the model above! There are two gateways marked with red in picture.

The gateway has two roles:

- hardware gateway (when you define IoB constraints);

- software gateways (when you don't define IoB constraints);

You need to make a mixed model approach, as shown above...

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Registered: ‎04-28-2020

Multumesc mult de raspuns.

 

Unfortunately, I have a new error I don't know how to address: 

"The S-function 'sysgen' in 'fpga_test4/fpga_test4 hwcosim' does not have TLC. TLC is required for this S-function because it permits constant sample times on its ports"

I hope we can solve it

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What versions of Matlab - Simulink and Vivado Design Suite do you use? When I first set up Basys 3, I have used Matlab - Simulink R2018b, and Vivado Design Suite 2019. I get the same error as you, when using two gateways on the same bus in parallel.

Try Matlab - Simulink R2015a, and Vivado Design Suite 2016. This worked for me! Also, very important, make sure that the workspace is set correctly! Make sure that you run Matlab from the System Generator Shortcut As Administrator! Otherwise a lot of frustrating errors will occur...

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I have Matlab 2017b and Vivado 2018.2, I hope they are fine

 

I will try to change the workspace to the project folder.

I have also changed the "System generator" -> "target directory" to my project folder, hopefully it helps...

This is a tough battle ... 

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It's the Matlab and Vivado version...

The Later version does not support "legacy boards". Try to use older versions, they always work best ever than the newer ones! Vivado 2016.2 and Matlab - Simulink 2015a! I have setted up succesfully Basys 3 hardware co-simulation with these versions! I hope it will help!

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