02-22-2021 06:32 PM
I was trying to design a DDC filter that use an FIR decimator.
In my system, the Fs is 122.88MHz.
The signal passing through DDS is 2 decimated by FIR.
So, I expected an output sample rate 61.44MHz.
I got the desired result like the photo above.
I activated the "output_sample_period" option because I needed the "nd" port of the FIR Compiler.
I set a sample period "2" because sample was 2 decimated.
but an output sample rate was not changed.
The s_axis_data_tvalid is always "1".
How do I get the same result as the first photo in my design using the s_axis_data_tvalid pin?
** My test environments
Vivado 2018.3 / MATLAB R2018a
attached my .slx file.
02-23-2021 02:57 AM
Hi, Thank you for reply.
The problem is that after enabling FIR Compiler's sample_period, decimation is not applied to the output.
In the first picture, you can see that the "s_axis_data_tvalid" is not activated, the input is 122.88 and the output is 61.44.
However, in the second picture, the "s_axis_data_tvalid" was activated, and both the input and output were output as 122.88.
I want to get an output of 61.44 by enabling s_axis_data_tvalid.
02-23-2021 11:28 PM
It's still difficult to understand your question, but I think you have questions on the output sample period setting on the FIR Compiler. NOTE when Output Sample Period is selected, you can specify the number of clock cycles between output samples. So, if you select output sample period and set it to 2, which means the 2 clock cycles between output samples. Hope it helps.