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Explorer
Explorer
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Registered: ‎05-22-2008

Overclocked DDS

Hello,

 

Is there a way, or what is the correct way to overclock a Xilinx DDS core? I have a design that samples flow through the system at 50Msamples/second. I generate a variable frequency Cosine/Sine with a DDS being clocked at 50MHz, but then downstream I start processing my 50Msamples/second on a 200MHz clock.

 

For clock domain purposes, what I think I would like to do is clock the DDS at 200MHz, and when use the Clock enable pin to only enable it every 4th clock, thereby incrementing through the memory/lut at the same rate, using the sample phase increment. The documentation doesn't really address this case, and seems to treat CE like more of a Chip Enable type of signal then a Data enable type of signal.

 

I know I could just run the DDS at 200MHz with a slower phase increment, but to do so while maintaining the tuning resolution I need, I think that would increase the resource utilization.

Looking at the documentation, it indicates that multiple output channels are supported and that when using this functionality, you effectively time-divide the clock so each channel gets 1/Nth the increments. I'm thinking about using this option and just not connecting the 3 other outputs.

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