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paul12345
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Registered: ‎07-14-2020

PG256 5G SD-FEC LDPC Base Graph and Puncturing clarifications

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I have two questions/comments on PG256:

1)

PG256 has a section on page 51 titled "5G New Radio Block Length". It says to pad bits to be encoded to reach 22*Z, 10*Z, 9*Z, 8*Z, or 6*Z bits depending on the base graph selected. However, ETSI 38.212 Section 5.2.2 (Release 16) says:

"find the minimum value of Z in all sets of lifting sizes in Table 5.3.2-1, denoted as Zc, such that K * Zc >= K', and set K = 22*Zc for LDPC base graph 1 and K =10*Zc for LDPC base graph 2;"

In other words, K = 22*Z or 10*Z, but it is apparently not 9*Z, 8*Z, or 6*Z as mentioned in Xilinx PG256. While Kb can indeed be 22, 10, 9, 8, 6, my reading of the 3GPP spec suggests either the 3GPP release is vague, or PG256 is incorrect in the size K of the bits to be encoded. Perhaps whoever wrote that document could comment on who is correct and how much input padding is actually required.


2)

For my second question: could you please clarify the language "the first 2*Z information bits that are punctured should be removed from the start of the output block". I understand that the puncturing must happen, but is this saying that the IP has already removed these bits, or is it saying that the user is responsible for removing them in their own logic?

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @paul12345 ,

Sorry, i misread the question. I got your point now about why K=Kb*Zc. The reason why the SD_FEC chooses the information bits as K=Kb*Zc for base graph 2 rather than 10*Zc is explained in this AR:  https://www.xilinx.com/support/answers/71636.html 

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nathanx
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Registered: ‎08-01-2007

A1 -> I'm pretty sure PG256 is correct, do you look at the latest 3GPP spec?

nathanx_1-1626269355629.png

A2 -> The user needs to remove them in their own logic, due to that the output of the encoder contains all information and parity bits in 5G NR mode.

 

 

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paul12345
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Registered: ‎07-14-2020

Yes, ETSI 38.212 Release 16. It makes no mention of K = {9 | 8 | 6} * Zc, only K = {22 | 10} * Zc. But maybe it's a mistake in the spec?

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nathanx
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Registered: ‎08-01-2007

I think it's a mistake, are you able to talk to the author of the spec?

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @paul12345 ,

The SD-FEC IP is based on 3GPP 38.212 v15.0.0. The reference to this spec is provided in PG256 (page 121, under references).

This version of the spec mentions the K values as 9,8,6  in section 5.2.2.

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paul12345
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Registered: ‎07-14-2020

Did you actually read that document you referenced? It has the same flaw which I am asking about in this thread. Specifically, when it says how to compute K, it does *not* say (Kb * Zc) but rather it says (22 * Zc) or (10 * Zc) depending on the base graph. That is exactly what I'm asking about. Maybe it is implied through the LDPC definition that they mean that it should take (Kb * Zc), but that is not stated in the language of the document (15.0.0, 15.2.0, 16.0.0, etc. none of them say K = Kb * Zc) in section 5.2.2.

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @paul12345 ,

Sorry, i misread the question. I got your point now about why K=Kb*Zc. The reason why the SD_FEC chooses the information bits as K=Kb*Zc for base graph 2 rather than 10*Zc is explained in this AR:  https://www.xilinx.com/support/answers/71636.html 

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paul12345
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Registered: ‎07-14-2020

Excellent, so someone else has already noticed this discrepancy. So I guess the spec is not wrong and they do mean K = 10*Zc for base graph 2, and I just need to figure out how to zero pad the result appropriately given that Xilinx implemented K = Kb*Zc. Thanks for the link and response.

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