01-06-2019 01:38 PM
I'm trying to pass data from the Simulink blocks to the Xilinx blocks. These Simulink blocks deliver arrays and I get an error related to the sampling periods. How can i fix this? If my Gateways blocks are used to build a AXI STREAM INTERFACE. The overall FPGA clock period affects the speed of the AXI transactions?
My FPGA clock period is 2 ns
Simulink system period is 1 sec
Gateway in clock period: 1
In the following screenshots I show my design
01-07-2019 06:44 AM
The problem looks similar to https://forums.xilinx.com/t5/Video/Sample-rate-issues-with-counter-block/m-p/138858#M3796.
If this does not resolve issue, then can you please share the design as well.
01-07-2019 07:03 AM
Thanks for your reply. I will try this recommendation as soon as possible to me. If this work, I will let you know. Thanks again
01-08-2019 02:38 PM
I simplify a little my design to explain more easily the problem . In this new design I'm using the Xilinx block: FDATool to calculate the coefficients of the FIR Compiler 7.2
Here is a brief description about my design:
I'M using a signal source block which provide a audio signal sampled at 22050 Hz in frames of 1024 samples. This block can be founded as a source block in the DSP System Toolbox from Simulink. The audio signal is one of the default signals provided with this block. I need process a complete frame of this signals because this is a constraint of my design.
Gateway in blocks only process samples no buffers, so I understand that the sampling rate of the Gateway In block need to be more faster than the stream of samples before the Unbuffer block that I use to convert from frame based data to sample based data.
There is a information about the time configuration of my Sysgen Token:
Simulink System Period: 1/22050
FPGA clock period: 10 ns
I also check the recommendation posted before and my problem persists even if I follow the recommendation marked as a accepted solution.
In the following Simulink file I share my design. You need first open the FDATOOL block and press generate filter to compute the filter coefficients and then select the Export option under the File tap. Then Export the coefficients to Matlab work space under the Num name. The filter design could be anywhere, I'm interested in the sample time problem by this reason I'm using normalized sample rate.
I'M using Matlab R2017a and Vivado 2017.4
Thanks to anyone that read this post and leave a comment about the solution.
01-10-2019 10:47 AM
I have checked this and I am not able to see the error. Please see attached for the result.
Please let me know if there are multiple clocks in the design,
01-10-2019 07:09 PM
Thanks you for reply. In the design that I previously share the error appears as a malfunction in the filter block, check the another Spectrum Analyzer called Spectrum Analyzer. A friend with a little experience recommend me change the simulink clock period to 1/22050, and the compilation error disappear, but the problem of pass data from frame based blocks to Xilinx Gateway In blocks persists. I'M not using multiples clocks domains. You suggest use this technique to solve this issue? If I include the Xilinx FIR filter block in a new subsystem, the Simulink clock period of the token that corresponds with this new subsystem must be 1/22050 seconds? In this case what is the Simulink **bleep** period of the general Token. Is there any example that show the transfer data of frame based to xilinx Gateway in block? There is a screenshot that show the output of the Xilinx FIR filter block and the filter designed, note that the filter specifications are given in normalized sample time. Also I include a RAR with the simulink model and a .mat with the filter coefficients. Thanks again