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Registered: ‎04-20-2009

Pipeling My Design

I am trying to develop a fourth order fractional filter to meet speed. I want the design to run at 60 MHz but after I get my XST report the estimated clock speed is 24.8 MHz on my original design and when I manually insertpipe stage I can only improve the performance up to 39.2 MHz. But the is done manually. I am wondering is there a way I can have Accel DSP automatically pipeline my design through code so that the design can then meet  speed.
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